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GX1 Datasheet(PDF) 156 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 156 Page - National Semiconductor (TI) |
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156 / 247 page  www.national.com 156 Revision 1.0 Integrated Functions (Continued) 4.5.14 CS5530 Display Controller Interface As previously stated in Section 1.7 “Geode GX1/CS5530 System Designs” on page 13, the GX1 processor inter- faces with the Geode CS5530 I/O companion chip. This section will discuss the specifics on signal connections between the two devices with regards to the display con- troller. Because the GX1 processor is used in a system with the CS5530 I/O companion chip, the need for an external RAMDAC is eliminated. The CS5530 contains the DACs, a video accelerator engine, and a TFT interface. A GX1 processor and CS5530-based system supports both flat panel and CRT configurations. Figure 4-16 shows the signal connections for both types of systems. Figure 4-16. Display Controller Signal Connections DCLK PCLK FP_HSYNC FP_VSYNC ENA_DISP VID_RDY VID_CLK VID_DATA[7:0] PIXEL[17:12] (R) PIXEL[11:6] (G) HSYNC VSYNC R[5:0] G[5:0] B[5:0] CLK VDD 12VBKL Pin 13 Pin 14 Pin 3 Pin 2 Pin 1 Geode™ GX1 Processor Power Control TFT ENAB VGA Pin 15 Pin 12 Flat Geode™ CS5530 I/O Companion DCLK PCLK FP_HSYNC FP_VSYNC DISP_ENA VID_RDY VID_CLK VID_DATA[7:0] PIXEL[23:18] PIXEL[15:10] PIXEL[5:0] (B) VID_VAL CRT_HSYNC CRT_VSYNC PIXEL[7:2] VID_VAL HSYNC VSYNC FP_ENA_VDD FP_ENA_BKL FP_DISP_ENA_OUT FP_HSYNC FP_VSYNC FP_CLK FP_DATA[17:12] FP_DATA[11:16] FP_DATA[5:0] Logic HSYNC_OUT VSYNC_OUT IOUTR IOUTG IOUTB DDC_SCL DDC_SDA Panel Port Flat Panel Configuration CRT Configuration |
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