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Revision 1.0

Integrated Functions (Continued)

4.5.12 Palette Access Registers

These registers are used for accessing the internal palette

RAM and extensions. In addition to the standard 256

entries for 8-bpp color translation, the GX1 processor pal-

ette has extensions for cursor colors and overscan (border)

color.

The Palette Access register group consists of two 32-bit

registers

located

GX_BASE+8370h

and

GX_BASE+8374h. These registers are summarized in

Table4-28onpage141,and Table4-33gives theirbit for-

mats.

Table 4-33. Display Controller Palette

Bit

Name

Description

GX_BASE+8370h-8373h

DC_PAL_ADDRESS Register (R/W)

Default Value = xxxxxxxxh

31:9

RSVD

Reserved: Set to 0.

8:0

PALETTE_ADDR

Palette Address: The address to be used for the next access to the DC_PAL_DATA register. Each

access to the data register automatically increments the palette address register. If non-sequential

access is made to the palette, the address register must be loaded between each non-sequential

data block. The address ranges are as follows.

Address

Color

0h - FFh

Standard Palette Colors

100h

Cursor Color 0

101h

Cursor Color 1

102h

Reserved

103h

Reserved

104h

Overscan (Color Border)

105h - 1FFh

Not Valid

GX_BASE+8374h-8377h

DC_PAL_DATA Register (R/W)

Default Value = xxxxxxxxh

31:18

RSVD

Reserved: Set to 0.

17:0

PALETTE_DATA

Palette Data: The read or write data for a palette access.1

When a read or write to the palette RAM occurs, the previous output value is held for one additional DCLK period. This effect should

go unnoticed and provides for sparkle-free update. Prior to a read or write to this register, the DC_PAL_ADDRESS register should be

loaded with the appropriate address. The address automatically increments after each access to this register, so for sequential access,

the address register need only be loaded once

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