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Integrated Functions (Continued)

4.5.10 Timing Registers

The Display Controller’s timing registers control the gener-

ation of sync, blanking, and active display regions. They

providecompleteflexibility in interfacingtobothCRT and

flat panel displays. These registers will generally be pro-

grammed by the BIOS from an INT10h call or by the

extended mode driver from a display timing file. Note that

the horizontal timing parameters are specified in character

clocks, which actually means pixels divided by 8, since all

characters are bit mapped. For interlaced display the verti-

cal counter will be incremented twice during each display

line, so vertical timing parameters should be programmed

with reference to the total frame rather than a single field.

The Timing registers group consists of six 32-bit registers

located at GX_BASE+8330h-834Ch. These registers are

summarized in Table4-28onpage141,and Table4-31

gives their bit formats.

Table 4-31. Display Controller Timing Registers

Bit

Name

Description

GX_BASE+8330h-8333h

DC_H_TIMING_1 Register (R/W) (Locked)

Default Value = xxxxxxxxh

31:27

RSVD

Reserved: Set to 0.

26:19

H_TOTAL

Horizontal Total: The total number of character clocks for a given scan line minus 1. Note that the

value is necessarily greater than the H_ACTIVE field because it includes border pixels and blanked

pixels. For flat panels, this value will never change. The field [26:16] may be programmed with the

pixel count minus 1, although bits [18:16] are ignored. The horizontal total is programmable on 8-

pixel boundaries only.

18:16

IGRD

Ignored

15:11

RSVD

Reserved: Set to 0.

10:3

H_ACTIVE

Horizontal Active: The total number of character clocks for the displayed portion of a scan line

minus 1. The field [10:0] may be programmed with the pixel count minus 1, although bits [2:0] are

ignored. The active count is programmable on 8-pixel boundaries only. Note that for flat panels, if this

value is less than the panel active horizontal resolution (H_PANEL), the parameters

H_BLANK_START, H_BLANK_END, H_SYNC_START, and H_SYNC_END should be reduced by

the value of H_ADJUST (or the value of H_PANEL – H_ACTIVE / 2)to achieve horizontal centering.

2:0

IGRD

Ignored

Note:

For simultaneous CRT and flat panel display the H_ACTIVE and H_TOTAL parameters pertain to both.

GX_BASE+8334h-8337h

DC_H_TIMING_2 Register (R/W) (Locked)

Default Value = xxxxxxxxh

31:27

RSVD

Reserved: Set to 0.

26:19

H_BLK_END

Horizontal Blank End: The character clock count at which the horizontal blanking signal becomes

inactive minus 1. The field [26:16] may be programmed with the pixel count minus 1, although bits

[18:16] are ignored. The blank end position is programmable on 8-pixel boundaries only.

18:16

IGRD

Ignored

15:11

RSVD

Reserved: Set to 0.

10:3

H_BLK_START

Horizontal Blank Start: The character clock count at which the horizontal blanking signal becomes

active minus 1. The field [10:0] may be programmed with the pixel count minus 1, although bits [2:0]

are ignored. The blank start position is programmable on 8-pixel boundaries only.

2:0

IGRD

Ignored

Note:

A minimum of four character clocks are required for the horizontal blanking portion of a line in order for the timing generator to

function correctly.

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