GX1 datasheet(155/247 Pages) NSC

155 / 247 page

Revision 1.0

155

www.national.com

Integrated Functions (Continued)

4.5.13 FIFO Diagnostic Registers

The FIFO Diagnostic register group consists of two 32-bit

registers

located

GX_BASE+8378h

and

GX_BASE+837Ch. These registers are summarized in

Table 4-28 on page 141, and Table 4-34 gives their bit for-

mats

Table 4-34. FIFO Diagnostic Registers

Bit

Name

Description

GX_BASE+8378h-837Bh

DC_DFIFO_DIAG Register (R/W)

Default Value = xxxxxxxxh

31:0

DISPLAY FIFO

DIAGNOSTIC

DATA

Display FIFO Diagnostic Read or Write Data: Before this register is accessed, the DIAG bit in

DC_GENERAL_CFG register (see Table 4-29 on page 144) should be set high and the DFLE bit

should be set low. Since, each FIFO entry is 64 bits, an even number of write operations should be

performed. Each pair of write operations will cause the FIFO write pointer to increment automati-

cally. After all write operations have been performed, a single read of don't care data should be per-

formed to load data into the output latch. Each subsequent read will contain the appropriate data

which was previously written. Each pair of read operations will cause the FIFO read pointer to

increment automatically. A pause of at least four core clocks should be allowed between subse-

quent read operations to allow adequate time for the shift to take place.

GX_BASE+837Ch-837Fh

DC_CFIFO_DIAG Register (R/W)

Default Value = xxxxxxxxh

31:0

COMPRESSED

FIFO DIAGNOS-

TIC DATA

Compressed Data FIFO Diagnostic Read or Write Data: Before this register is accessed, the

DIAG bit in DC_GENERAL_CFG (see Table 4-29 on page 144) register should be set high and the

DFLE bit should be set low. Also, the DIAG bit in DC_OUTPUT_CFG (see Table 4-29 on Page 147)

should be set high and the CFRW bit in DC_OUTPUT_CFG should be set low. After each write, the

FIFO write pointer will automatically increment. After all write operations have been performed, the

CFRW bit of DC_OUTPUT_CFG should be set high to enable read addresses to the FIFO and a

single read of don't care data should be performed to load data into the output latch. Each subse-

quent read will contain the appropriate data which was previously written. After each read, the

FIFO read pointer will automatically increment.

GX1 Datasheet(PDF) 155 Page - National Semiconductor (TI)

GX1 Datasheet(HTML) 155 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL