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Instruction Set

This section summarizes the Geode GX1 processor

instruction set and provides detailed information on the

instruction encodings. The instruction set is divided into

four categories:

• Processor Core Instruction Set - listed in Table 8-27 on

page 223.

• FPU Instruction Set - listed in Table 8-29 on page 235.

• MMX Instruction Set - listed in Table 8-31 on page 240.

• Extended MMX Instruction Set - listed in Table 8-33 on

page 245.

These tables provide information on the instruction encod-

ing, and the instruction clock counts for each instruction.

The clock count values for these tables are based on the fol-

lowing assumptions

All clock counts refer to the internal processor core

clock frequency. For example, clock doubled GX1

processor cores will reference a clock frequency that is

twice the bus frequency.

The instruction has been prefetched, decoded and is

ready for execution.

Bus cycles do not require wait states.

There are no local bus HOLD requests delaying

processor access to the bus.

No exceptions are detected during instruction execu-

tion.

If an effective address is calculated, it does not use

two general register components. One register, scaling

and displacement can be used within the clock count

shown. However, if the effective address calculation

uses two general register components, add one clock

to the clock count shown.

All clock counts assume aligned 32-bit memory/ IO

operands.

If instructions access a 32-bit operand on odd

addresses, add one clock for read or write and add two

clocks for read and write.

For non-cached memory accesses, add two clocks

(clock doubled GX1 processor cores) or four clocks

(clock tripled GX1 processor cores), assuming zero wait

state memory accesses.

10. Locked cycles are not cacheable. Therefore, using the

LOCK prefix with an instruction adds additional clocks

as specified in item 9 above.

8.1

GENERAL INSTRUCTION SET FORMAT

Depending on the instruction, the GX1 processor core

instructions follow the general instruction format shown in

Table 8-1.

These instructions vary in length and can start at any byte

address. An instruction consists of one or more bytes that

can include prefix bytes, at least one opcode byte, a mod

r/m byte, an s-i-b byte, address displacement, and imme-

diate data. An instruction can be as short as one byte and

as long as 15 bytes. If there are more than 15 bytes in the

instruction, a general protection fault (error code 0) is gen-

erated.

The fields in the general instruction format at the byte level

are summarized in Table 8-2 and detailed in the following

subsections.

Table 8-1. General Instruction Set Format

Prefix (optional)

Opcode

Address

Displacement

Immediate

Data

mod r/m Byte

s-i-b Byte

mod

reg

r/m

index

base

0 or More Bytes

1 or 2 Bytes

7:6

5:3

2:0

7:6

5:3

2:0

0, 8, 16, or 32

Bits

0, 8, 16, or 32

Bits

Table 8-2. Instruction Fields

Field Name

Description

Prefix (optional)

Prefix Field(s): One or more optional fields that are used to specify segment register override, address

and operand size, repeat elements in string instruction, LOCK# assertion.

Opcode

Opcode Field: Identifies instruction operation.

mod

Address Mode Specifier: Used with r/m field to select addressing mode.

reg

General Register Specifier: Uses reg, sreg3 or sreg2 encoding depending on opcode field.

r/m

Address Mode Specifier: Used with mod field to select addressing mode.

Scale factor: Determines scaled-index address mode.

index

Index: Determines general register to be used as index register.

base

Base: Determines general register to be used as base register.

Address Displacement

Displacement: Determines address displacement.

Immediate Data

Immediate Data: Immediate data operand used by instruction.

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