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GX1 Datasheet(PDF) 215 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 215 Page - National Semiconductor (TI) |
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215 / 247 page ![]() Revision 1.0 215 www.national.com Instruction Set (Continued) 8.1.2.3 s Field (Immediate Data Field Size) When used, the 1-bit s field determines the size of the immediate data field. If the s bit is set, the immediate field of the opcode is 8 bits wide and is sign-extended to match the operand size of the opcode. See Table 8-6. 8.1.2.4 eee Field (MOV-Instruction Register Selection) The eee field (bits [5:3]) is used to select the control, debug and test registers in the MOV instructions. The type of reg- ister and base registers selected by the eee field are listed in Table 8-7. The values shown in Table 8-7 are the only valid encodings for the eee bits. 8.1.3 mod and r/m Byte (Memory Addressing) The mod and r/m fields within the mod r/m byte, select the type of memory addressing to be used. Some instructions use a fixed addressing mode (e.g., PUSH or POP) and therefore, these fields are not present. Table 8-8 lists the addressing method when 16-bit addressing is used and a mod r/m byte is present. Some mod r/m field encodings are dependent on the w field and are shown in Table 8-9. Table 8-6. s Field Encoding s Field Immediate Field Size 8-Bit Operand Size 16-Bit Operand Size 32-Bit Operand Size 0 (or not present) 8bits 16bits 32 bits 18 bits 8 bits (sign- extended) 8bits (sign- extended) Table 8-7. eee Field Encoding eee Field Register Type Base Register 000 Control Register CR0 010 Control Register CR2 011 Control Register CR3 100 Control Register CR4 000 Debug Register DR0 001 Debug Register DR1 010 Debug Register DR2 011 Debug Register DR3 110 Debug Register DR6 111 Debug Register DR7 011 Test Register TR3 100 Test Register TR4 101 Test Register TR5 110 Test Register TR6 111 Test Register TR7 Table 8-8. mod r/m Field Encoding mod Field r/m Field 16-Bit Address Mode with mod r/m Byte1 1. d8 refers to 8-bit displacement, d16 refers to 16-bit displace- ment, and d32 refers to a 32-bit displacement. 32-Bit Address Mode with mod r/m Byte and No s-i-b Byte Present1 00 000 DS:[BX+SI] DS:[EAX] 00 001 DS:[BX+DI] DS:[ECX] 00 010 SS:[BP+SI] DS:[EDX] 00 011 SS:[BP+DI] DS:[EBX] 00 100 DS:[SI] s-i-b is present (See Table 8-15) 00 101 DS:[DI] DS:[d32] 00 110 DS:[d16] DS:[ESI] 00 111 DS:[BX] DS:[EDI] 01 000 DS:[BX+SI+d8] DS:[EAX+d8] 01 001 DS:[BX+DI+d8] DS:[ECX+d8] 01 010 SS:[BP+SI+d8] DS:[EDX+d8] 01 011 SS:[BP+DI+d8] DS:[EBX+d8] 01 100 DS:[SI+d8] s-i-b is present (See Table 8-15) 01 101 DS:[DI+d8] SS:[EBP+d8] 01 110 SS:[BP+d8] DS:[ESI+d8] 01 111 DS:[BX+d8] DS:[EDI+d8] 10 000 DS:[BX+SI+d16] DS:[EAX+d32] 10 001 DS:[BX+DI+d16] DS:[ECX+d32] 10 010 SS:[BP+SI+d16] DS:[EDX+d32] 10 011 SS:[BP+DI+d16] DS:[EBX+d32] 10 100 DS:[SI+d16] s-i-b is present (See Table 8-15) 10 101 DS:[DI+d16] SS:[EBP+d32] 10 110 SS:[BP+d16] DS:[ESI+d32] 10 111 DS:[BX+d16] DS:[EDI+d32] 11 xxx See Table 8-9. See Table 8-9 |
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