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GX1 Datasheet(PDF) 219 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 219 Page - National Semiconductor (TI) |
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219 / 247 page  Revision 1.0 219 www.national.com Instruction Set (Continued) 8.2.1.2 CPUID Instruction with EAX = 0000 0001h Standard function 01h (EAX = 1) of the CPUID instruction returns the processor type, family, model, and stepping information of the current processor in the EAX register (see Table 8-18). The EBX and ECX registers are reserved. The standard feature flags supported are returned in the EDX register as shown in Table 8-19. Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features have protection con- trol in CR4. Before using any of these features on the pro- cessor, the software should check the corresponding feature flag. Attempting to execute an unavailable feature can cause exceptions and unexpected behavior. For exam- ple, software must check EDX bit 4 before attempting to use the Time Stamp Counter instruction. 8.2.1.3 CPUID Instruction with EAX = 00000002h Standard function 02h (EAX = 02h) of the CPUID instruc- tion returns information that is specific to the National Semiconductor family of processors. Information about the TLB is returned in EAX as shown in Table 8-20. Information about the L1 cache is returned in EDX. Table 8-18. EAX, EBX, ECX CPUID Data Returned when EAX = 1 Register Returned Contents Description EAX[3:0] xx Stepping ID EAX[7:4] 4 Model EAX[11:8] 5 Family EAX[15:12] 0 Type EAX[31:16] - Reserved EBX - Reserved ECX - Reserved Table 8-19. EDX CPUID Data Returned when EAX = 1 EDX Returned Content1 Feature Flag CR4 Bit EDX[0] 1 FPU On-Chip - EDX[1] 0 Virtual Mode Extension - EDX[2] 0 Debug Extensions - EDX[3] 0 Page Size Extensions - EDX[4] 1 Time Stamp Counter 2 EDX[5] 1 RDMSR / WRMSR Instructions - EDX[6] 0 Physical Address Extensions - EDX[7] 0 Machine Check Excep- tion - EDX[8] 1 CMPXCHG8B Instruction - EDX[9] 0 On-Chip APIC Hardware - EDX[10] 0 Reserved - EDX[11] 0 SYSENTER / SYSEXIT Instructions - EDX[12] 0 Memory Type Range Registers - EDX[13] 0 Page Global Enable - EDX[14] 0 Machine Check Architecture - EDX[15] 1 Conditional Move Instructions - EDX[16] 0 Page Attribute Table - EDX[22:17] 0 Reserved - EDX[23] 1 MMX Instructions - EDX[24] 0 Fast FPU Save and Restore - EDX[31:25] 0 Reserved - 1. 0 = Not Supported Table 8-20. Standard CPUID with EAX = 00000002h Register Returned Contents Description EAX xx xx 70 xxh TLB is 32 entry, 4-way set asso- ciative, and has 4 KB pages. EAX xx xx xx 01h The CPUID instruction needs to be executed only once with an input value of 02h to retrieve com- plete information about the cache and TLB. EBX Reserved ECX Reserved EDX xxxxxx80h L1 cacheis16KB, 4-wayset associated, and has 16 bytes per line. Table 8-19. EDX CPUID Data Returned when EAX = 1 (Continued) EDX Returned Content1 Feature Flag CR4 Bit |
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