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GX1 Datasheet(PDF) 244 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # GX1
Description  Processor Series Low Power Integrated x86 Solution
PDF  247 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

GX1 Datasheet(HTML) 244 Page - National Semiconductor (TI)

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244
Revision 1.0
Instruction Set (Continued)
8.6
EXTENDED MMX INSTRUCTION SET
National Semiconductor has added instructions to its
implementation of the Intel MMX architecture in order to
facilitate writing of multimedia applications. In general,
these instructions allow more efficient implementation of
multimedia algorithms, or more precision in computation
than can be achieved using the basic set of MMX instruc-
tions. All of the added instructions follow the SIMD (single
instruction, multiple data) format. Many of the instructions
add flexibility to the MMX architecture by allowing both
source operands of an instruction to be preserved, while
the result goes to a separate register that is derived from
the input.
Table 8-33 summarizes the Extended MMX Instructions.
Theabbreviationsusedin the tableare listed in Table8-32.
Configuration control register CCR7(0) at Index EBh (see
Table 3-11 on Page 53) must be set to allow the execution
of the Extended MMX instructions.
Table 8-32. Extend MMX Instruction Set
Table Legend
Abbreviation
Description
<----
Result written.
[11 mm reg]
Binary or binary groups of digits.
mm
One of eight 64-bit MMX registers.
reg
A general purpose register.
<--sat--
If required, the resultant data is saturated to
remain in the associated data range.
<--move--
Source data is moved to result location.
[byte]
Eight 8-bit BYTEs are processed in parallel.
[word]
Four 16-bit WORDs are processed in
parallel.
[dword]
Two 32-bit DWORDs are processed in
parallel.
[qword]
One 64-bit QWORD is processed.
[sign xxx]
The BYTE, WORD, DWORD or QWORD
most significant bit is a sign bit.
mm1, mm2
MMX Register 1, MMX Register 2.
mod r/m
Mod and r/m byte encoding (Table 8-15 on
page 217).
pack
Source data is truncated or saturated to
next smaller data size, then concatenated.
packdw
Pack two DWORDs from source and two
DWORDs from destination into QWORDs in
destination register.
packwb
Pack QWORDs from source and QWORDs
from destination into eight BYTEs in desti-
nation register.



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