SC1100 datasheet(176/348 Pages) NSC

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176

Revision 1.1

Core Logic Module (Continued)

Index 6Eh-6Fh

ROM Mask Register (R/W)

Reset Value: FFF0h

15:8

Reserved. Must be set to FFh.

7:4

ROM Size. If F0 Index 52h[2] = 1:

0000: 16 MB = FF000000h-FFFFFFFFh

1000: 8 MB = FF800000h-FFFFFFFFh

1100: 4 MB = FFC00000h-FFFFFFFFh

1110: 2 MB = FFE00000h-FFFFFFFFh

1111: 1 MB = FFF00000h-FFFFFFFFh

All other settings for these bits are reserved.

3:0

Reserved. Must be set to 0.

Index 70h-71h

IOCS1# Base Address Register (R/W)

Reset Value: 0000h

15:0

I/O Chip Select 1 Base Address. This 16-bit value represents the I/O base address used to enable assertion of IOCS1#

(ball D22, muxed with GPIO14+IOR#+DOCR# see PMR[21,2] in Table 3-2 on page 50 for ball function selection).

This register is used in conjunction with F0 Index 72h (IOCS1# Control register).

Index 72h

IOCS1# Control Register (R/W)

Reset Value: 00h

This register is used in conjunction with F0 Index 70h (IOCS1# Base Address register).

I/O Chip Select 1 Positive Decode (IOCS1#).

0: Disable.

1: Enable.

Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0

Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.

0: Disable.

1: Enable.

Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0

Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.

0: Disable.

1: Enable.

4:0

IOCS1# I/O Address Range. This 5-bit field is used to select the range of IOCS1#.

00000: 1 Byte

01111: 16 Bytes

00001: 2 Bytes

11111: 32 Bytes

00011: 4 Bytes

All other combinations are reserved.

00111: 8 Bytes

Index 73h

Reserved

Reset Value: 00h

Index 74h-75h

IOCS0# Base Address Register (R/W)

Reset Value: 0000h

15:0

I/O Chip Select 0 Base Address. This 16-bit value represents the I/O base address used to enable the assertion of

IOCS0# (ball B23, muxed with GPIO17+IOCHRDY, see PMR[9,5] in Table 3-2 on page 50 for ball function selection).

This register is used in conjunction with F0 Index 76h (IOCS0# Control register).

Index 76h

IOCS0# Control Register (R/W)

Reset Value: 00h

This register is used in conjunction with F0 Index 74h (IOCS0# Base Address register).

I/O Chip Select 0 Positive Decode (IOCS0#).

0: Disable.

1: Enable.

Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0

Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.

0: Disable.

1: Enable.

Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0

Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.

0: Disable.

1: Enable.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

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SC1100 Datasheet(PDF) 176 Page - National Semiconductor (TI)

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