SC1100 datasheet(174/348 Pages) NSC

174 / 348 page

www.national.com

174

Revision 1.1

Core Logic Module (Continued)

Keyboard Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O Ports 060h and

064h (as well as 062h and 066h, if enabled - F4 Index 5Bh[7] = 1).

0: Subtractive.

1: Positive.

Note:

If F0BAR1+I/O Offset 10h bits 10 = 0 and 16 = 1, then this bit must be written 0.

Real -Time Clock Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O Ports 070h-073h.

0: Subtractive.

1: Positive.

Index 5Bh

Decode Control Register 2 (R/W)

Reset Value: 20h

Note:

Positive decoding by the Core Logic module speeds up the I/O cycle time. The Keyboard, LPT3, LPT2, and LPT1 I/O ports do

not exist in the Core Logic module. It is assumed that if positive decoding is enabled for any of these ports, the port exists on

the ISA bus.

Keyboard I/O Port 062h/066h Positive Decode. This alternate port to the keyboard controller is provided in support of

power management features.

0: Disable.

1: Enable.

Reserved. Must be set to 0.

BIOS ROM Positive Decode. Selects PCI positive or subtractive decoding for accesses to the configured ROM space.

0: Subtractive.

1: Positive.

ROM configuration is at F0 Index 52h[2:0].

Secondary IDE Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 170h-

177h and 376h-377h (excluding writes to 377h).

0: Subtractive. Subtractively decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are

then forwarded to ISA.

1: Positive. Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus.

Primary IDE Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 1F0h-

1F7h and 3F6h-3F7h (excluding writes to 3F7h).

0: Subtractive. Subtractively decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are

then forwarded to ISA.

1: Positive. Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus.

LPT3 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 278h-27Fh.

0: Subtractive.

1: Positive.

LPT2 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 378h-37Fh.

0: Subtractive.

1: Positive.

LPT1 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3BCh-3BFh

0: Subtractive.

1: Positive.

Index 5Ch

PCI Interrupt Steering Register 1 (R/W)

Reset Value: 00h

Indicates target interrupts for signals INTB# (ball W24) and INTA# (ball AD26).

Note:

The target interrupt must first be configured as level sensitive via I/O Ports 4D0h and 4D1h in order to maintain PCI interrupt

compatibility.

7:4

INTB# (Ball W24) Target Interrupt.

0000: Disable

0100: IRQ4

1000: Reserved

1100: IRQ12

0001: IRQ1

0101: IRQ5

1001: IRQ9

1101: Reserved

0010: Reserved

0110: IRQ6

1010: IRQ10

1110: IRQ14

0011: IRQ3

0111: IRQ7

1011: IRQ11

1111: IRQ15

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

SC1100 Datasheet(PDF) 174 Page - National Semiconductor (TI)

SC1100 Datasheet(HTML) 174 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL