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170

Revision 1.1

Core Logic Module (Continued)

Index 43h

Delayed Transactions Register (R/W)

Reset Value: 02h

7:5

Reserved. Must be set to 0.

Enable PCI Delayed Transactions for Access to I/O Address 170h-177h (Secondary IDE Channel). PIO mode uses

repeated I/O transactions that are faster when non-delayed transactions are used.

0: I/O addresses complete as fast as possible on PCI. (Default)

1: Accesses to Secondary IDE channel I/O addresses are delayed transactions on PCI.

Enable PCI Delayed Transactions for Access to I/O Address 1F0h-1F7h (Primary IDE Channel). PIO mode uses

repeated I/O transactions that are faster when non-delayed transactions are used.

0: I/O addresses complete as fast as possible on PCI. (Default)

1: Accesses to Primary IDE channel I/O addresses are delayed transactions on PCI.

Enable PCI Delayed Transactions for AT Legacy PIC I/O Addresses. Some PIC status reads are long. Enabling delayed

transactions help reduce DMA latency for high bandwidth devices like VIP.

0: PIC I/O addresses complete as fast as possible on PCI. (Default)

1: Accesses to PIC I/O addresses are delayed transactions on PCI.

Enable PCI Delayed Transactions for AT Legacy PIT I/O Addresses. Some x86 programs (certain benchmarks/diagnos-

tics) assume a particular latency for PIT accesses; this bit allows that code to work.

0: PIT I/O addresses complete as fast as possible on PCI.

1: Accesses to PIT I/O addresses are delayed transactions on PCI. (Default)

For best performance (e.g., when running Microsoft Windows), this bit should be set to 0.

Reserved. Must be set to 0.

Index 44h

Reset Control Register (R/W)

Reset Value: 01h

AC97 Soft Reset. Active high reset for the AC97 codec interface.

0: AC97_RST# (ball AF23) is driven high. (Default)

1: AC97_RST# (ball AF23) is driven low.

6:4

Reserved. Must be set to 0.

IDE Controller Reset. Reset the IDE controller.

0: Disable.

1: Enable.

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

IDE Reset. Reset IDE bus.

0: Disable.

1: Enable (drives outputs to zero).

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

PCI Reset. Reset PCI bus.

0: Disable.

1: Enable.

When this bit is set to 1, the Core Logic module output signal PCIRST# is asserted and all devices on the PCI bus (including

PCIUSB) are reset. No other function within the Core Logic module is affected by this bit.

Write 0 to clear this bit. This bit is level-sensitive and must be cleared after the reset is enabled.

X-Bus Warm Start. Writing and reading this bit each have different meanings.

When reading this bit, it indicates whether or not a warm start occurred since power-up:

0: A warm start occurred.

1: No warm start has occurred.

When writing this bit, it can be used to trigger a system-wide reset:

0: No effect.

1: Execute system-wide reset (used only for clock configuration at power-up).

Index 45h

Reserved

Reset Value: 00h

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

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