SC1100 datasheet(171/348 Pages) NSC

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Core Logic Module (Continued)

Index 46h

PCI Functions Enable Register (R/W)

Reset Value: FEh

7:6

Reserved. Resets to 11.

F5 (PCI Function 5). When asserted (set to 1), enables the register space designated as F5.

This bit must always be set to 1. (Default)

Reserved. Must be set to 0.

F3 (PCI Function 3). When asserted (set to 1), enables the register space designated as F3.

This bit must always be set to 1. (Default)

F2 (PCI Function 2). When asserted (set to 1), enables the register space designated as F2.

This bit must always be set to 1. (Default)

F1 (PCI Function 1). When asserted (set to 1), enables the register space designated as F1.

This bit must always be set to 1. (Default)

Reserved. Must be set to 0.

Index 47h

Miscellaneous Enable Register (R/W)

Reset Value: 00h

7:3

Reserved. Must be set to 0.

F0BAR1 (PCI Function 0, Base Address Register 1). F0BAR1, pointer to I/O mapped LPC configuration registers.

0: Disable.

1: Enable.

F0BAR0 (PCI Function 0, Base Address Register 0). F0BAR0, pointer to I/O mapped GPIO configuration registers.

0: Disable.

1: Enable.

Reserved. Must be set to 0.

Index 48h-4Bh

Reserved

Reset Value: 00h

Index 4Ch-4Fh

Top of System Memory (R/W)

Reset Value: FFFFFFFFh

31:0

Top of System Memory. Highest address in system used to determine active decode for external PCI mastered memory

cycles.

If an external PCI master requests a memory address below the value programmed in this register, the cycle is transferred

from the external PCI bus interface to the Fast-PCI interface for servicing by the GX1 module.

Note:

The 4 least significant bits must be set to 1.

Index 50h

PIT Control/ISA CLK Divider (R/W)

Reset Value: 7Bh

PIT Software Reset.

0: Disable.

1: Enable.

PIT Counter 1.

0: Forces Counter 1 output (OUT1) to zero.

1: Allows Counter 1 output (OUT1) to pass to the Port 061h[4].

PIT Counter 1 Enable.

0: Sets GATE1 input low.

1: Sets GATE1 input high.

PIT Counter 0.

0: Forces Counter 0 output (OUT0) to zero.

1: Allows Counter 0 output (OUT0) to pass to IRQ0.

PIT Counter 0 Enable.

0: Sets GATE0 input low.

1: Sets GATE0 input high.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

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