SC1100 datasheet(169/348 Pages) NSC

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Core Logic Module (Continued)

Index 40h

PCI Function Control Register 1 (R/W)

Reset Value: 39h

7:6

Reserved. Must be set to 0.

Reserved. Must be set to 1.

Reserved. Must be set to 0.

PERR# Signals SERR#. Assert SERR# when PERR# is asserted or detected as active by the Core Logic module (allows

PERR# assertion to be cascaded to NMI (SMI) generation in the system).

0: Disable.

1: Enable.

PCI Interrupt Acknowledge Cycle Response. The Core Logic module responds to PCI interrupt acknowledge cycles.

0: Disable.

1: Enable.

Index 41h

PCI Function Control Register 2 (R/W)

Reset Value: 00h

7:6

Reserved. Must be set to 0.

X-Bus Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function

5 (F5) register space, an SMI is generated.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

Reserved. Must be set to 0.

XpressAUDIO Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI

Function 3 (F3) register space, an SMI is generated.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

IDE Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 2

(F2) register space, an SMI is generated.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

Power Management Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in

PCI Function 1 (F1) register space, an SMI is generated.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

Legacy Configuration SMI. If this bit is set to 1 and an access occurs to one of the configuration registers in the ISA Leg-

acy I/O register space, an SMI is generated.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].

Index 42h

Reserved

Reset Value: 00h

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

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