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Core Logic Module (Continued)

5.4

CHIPSET REGISTER SPACE

The Chipset Register Space of the Core Logic module is

comprised of five separate functions (F0-F3 and F5, note

that F4 is reserved), each with its own register space. Base

Address Registers (BARs) in each PCI header register

space set the base address for the configuration registers

for each respective function. The configuration registers

accessed through BARs are I/O or memory mapped. The

PCI header registers in all functions are very similar.

Function 0 (F0): PCI Header/Bridge Configuration

Registers for GPIO, and LPC Support (see Section

5.4.1).

Function 1 (F1): PCI Header Registers for SMI Status

and ACPI Support (see Section 5.4.2 on page 207).

Function 2 (F2): PCI Header/Channel 0 and 1 Configu-

ration Registers for IDE Controller Support (see Sec-

tion 5.4.3 on page 225).

Function 3 (F3): PCI Header Registers for XpressAU-

DIO Audio Support (see Section 5.4.4 on page 231).

Function 4 (F4): Reserved.

Function 5 (F5): PCI Header Registers for X-Bus

Expansion Support (see Section 5.4.5 on page 246).

Function 5 contains six BARs in their standard PCI

header locations (i.e., Index 10h, 14h, 18h, 1Ch, 20h,

and 24h). In addition there are six mask registers that

allow the six BARs to be fully programmable from 4

GB to 16 bytes for memory and from 4 GB to 4 bytes

for I/O.

General Remarks:

• Reserved bits that are defined as "must be set to 0 or 1"

should be written with that value.

• Reserved bits that are not defined as "must be set to 0

or 1" should be written with a value that is read from

them.

• "Read to Clear" registers that are wider than one byte

should be read in one read operation. If they are read a

byte at a time, status bits may be lost, or not cleared.

5.4.1

Bridge, GPIO, and LPC Registers - Function 0

The register space designated as Function 0 (F0) is used

to configure Bridge features and functionality unique to the

Core Logic module. In addition, it configures the PCI por-

tion of support hardware for the GPIO and LPC support

registers. The bit formats for the PCI Header and Bridge

Configuration registers are given in Table 5-29.

Note:

The registers at F0 Index 50h-FFh can also be

accessed at F1BAR0+I/O Offset 50h-FFh. How-

ever, the preferred method is to program these reg-

isters through the F0 register space.

Located in the PCI Header registers of F0, are two Base

Address Registers (F0BARx) used for pointing to the regis-

ter spaces designated for GPIO and LPC configuration

(described in Section 5.4.1.1 "GPIO Support Registers" on

page 196 and Section 5.4.1.2 "LPC Support Registers" on

page 200).

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value: 100Bh

Index 02h-03h

Device Identification Register (RO)

Reset Value: 0510h

Index 04h-05h

PCI Command Register (R/W)

Reset Value: 000Fh

15:10

Reserved. Must be set to 0.

Fast Back-to-Back Enable. This function is not supported when the Core Logic module is a master. It must always be dis-

abled (i.e., must be set to 0).

SERR#. Allow SERR# assertion on detection of special errors.

0: Disable. (Default)

1: Enable.

Wait Cycle Control (Read Only). This function is not supported in the Core Logic module. It is always disabled (always

reads 0, hardwired).

Parity Error. Allow the Core Logic module to check for parity errors on PCI cycles for which it is a target and to assert

PERR# when a parity error is detected.

0: Disable. (Default)

1: Enable.

VGA Palette Snoop Enable. (Read Only) This function is not supported in the Core Logic module. It is always disabled

(always reads 0, hardwired).

Memory Write and Invalidate. Allow the Core Logic module to do memory write and invalidate cycles, if the PCI Cache

Line register (F0 Index 0Ch) is set to 32 bytes (08h).

0: Disable. (Default)

1: Enable.

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