 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SC1100 Datasheet(PDF) 175 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
SC1100 Datasheet(HTML) 175 Page - National Semiconductor (TI) |
|
|
175 / 348 page  Revision 1.1 175 www.national.com Core Logic Module (Continued) 3:0 INTA# (Ball AD26) Target Interrupt. 0000: Disable 0100: IRQ4 1000: Reserved 1100: IRQ12 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15 Index 5Dh PCI Interrupt Steering Register 2 (R/W) Reset Value: 00h Indicates target interrupts for signals INTD# (ball V24) and INTC# (ball Y24). Note that INTC# is muxed with GPIO19 (selection made via PMR[4], see Table 3-2 on page 50 for PMR[4] bit description). Note: The target interrupt must first be configured as level sensitive via I/O Ports 4D0h and 4D1h in order to maintain PCI interrupt compatibility. 7:4 INTD# (Ball V24) Target Interrupt. 0000: Disable 0100: IRQ4 1000: Reserved 1100: IRQ12 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15 3:0 INTC (Ball Y24) Target Interrupt. 0000: Disable 0100: IRQ4 1000: Reserved 1100: IRQ12 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15 Index 5Eh-5Fh Reserved Reset Value: 00h Index 60h-63h ACPI Control Register (R/W) Reset Value: 00000000h 31:8 Reserved. Must be set to 0. 7 Internal SUSP_3V Shut Down PLL5. Allow internal SUSP_3V to shut down PLL5. 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 6 SUSP_3V Shut Down PLL4. Allow internal SUSP_3V to shut down PLL4. 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 5 SUSP_3V Shut Down PLL3. Allow internal SUSP_3V to shut down PLL3. 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 4 Reserved. 3 SUSP_3V Shut Down FMUL3. Allow internal SUSP_3V to shut down FMUL3. 0: Clock generator is stopped when internal SUSP_3V is active. 1: Clock generator continues working when internal SUSP_3V is active. 2 ACPI C3 SUSP_3V Enable. Allow internal SUSP_3V to be active during C3 state. 0: Disable. 1: Enable. 1 ACPI SL1 SUSP_3V Enable. Allow internal SUSP_3V to be active during SL1 sleep state. 0: Disable. 1: Enable. 0 ACPI C3 Support Enable. Allow support of C3 states. 0: Disable. 1: Enable. Index 64h-6Dh Reserved Reset Value: 00h Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
