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SC1100 Datasheet(PDF) 132 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 132 Page - National Semiconductor (TI) |
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132 / 348 page ![]() www.national.com 132 Revision 1.1 Core Logic Module (Continued) 5.2.7 I/O Ports 092h and 061h System Control The Core Logic module supports control functions of I/O Ports 092h (Port A) and 061h (Port B) for PS/2 compatibil- ity. I/O Port 092h allows a fast assertion of the A20M# or CPU_RST. (CPU_RST is an internal signal that resets the CPU. It is asserted for 100 µs after the negation of POR#.) I/O Port 061h controls NMI generation and reports system status.The Core Logic module generates an SMI for every internal change of the A20M# state and the SMI handler sets the A20M# state inside the GX1 module. This method is used for both the Port 092h (PS/2) and Port 061h (key- board) methods of controlling A20M#. 5.2.7.1 I/O Port 092h System Control I/O Port 092h allows for a fast keyboard assertion of an A20# SMI and a fast keyboard CPU reset. Decoding for this register may be disabled via F0 Index 52h[3]. The assertion of a fast keyboard A20# SMI is controlled by either I/O Port 092h or by monitoring for the keyboard com- mand sequence (see Section 5.2.8.1 "Fast Keyboard Gate Address 20 and CPU Reset" on page 133). If bit 1 of I/O Port 092h is cleared, the Core Logic module internally asserts an A20M#, which in turn causes an SMI to the GX1 module. If bit 1 is set, A20M# is internally deasserted, again causing an SMI. The assertion of a fast keyboard reset (WM_RST SMI) is controlled by bit 0 in I/O Port 092h or by monitoring for the keyboard command sequence (write data = FEh to I/O port 64h). If bit 0 is changed from 0 to 1, the Core Logic module generates a reset to the GX1 module by generating a WM_RST SMI. When the WM_RST SMI occurs, the BIOS jumps to the Warm Reset vector. Note that Warm Reset is not a pin, it is under SMI control. 5.2.7.2 I/O Port 061h System Control Through I/O Port 061h, the speaker output can be enabled, the status of IOCHK and SERR can be read, and the state of the speaker data (Timer2 output) and refresh toggle (Timer1 output) can be read back. 5.2.7.3 SMI Generation for NMI Figure 5-10 shows how the Core Logic module can gener- ate an SMI for an NMI. Note that NMI is not a pin. |
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