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SC1100 Datasheet(PDF) 133 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 133 Page - National Semiconductor (TI) |
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133 / 348 page ![]() Revision 1.1 133 www.national.com Core Logic Module (Continued) 5.2.8 Keyboard Support The Core Logic module can actively decode the keyboard controller I/O Ports 060h, 062h, 064h and 066h, and gener- ate an LPC bus cycle. Keyboard positive decoding can be disabled if F0 Index 5Ah[1] is cleared (i.e., subtractive decoding enabled). Access to I/O Ports 060h and 064h on Sub-ISA can be enabled with ROMCS# asserted, by setting bit F0 Index 53h[7]. The Core Logic module will also actively decode the keyboard controller I/O Ports 062h and 066h if F0 Index 5Bh[7] is set. 5.2.8.1 Fast Keyboard Gate Address 20 and CPU Reset The Core Logic module monitors the keyboard I/O Ports 064h and 060h for the fast keyboard A20M# and CPU reset control sequences. If a write to I/O Port 060h[1] = 1 after a write takes place to I/O Port 064h with data of D1h, then the Core Logic module asserts the A20M# signal. A20M# remains asserted until cleared by any one of the following: • A write to bit 1 of I/O Port 092h. • A CPU reset of some kind. • A write to I/O Port 060h[1] = 0 following a write to I/O Port 064h with data of D1h. The fast keyboard A20M# and CPU reset can be disabled through F0 Index 52h[7]. By default, bit 7 is set, and the fast keyboard A20M# and CPU reset monitor logic is active. If bit 7 is clear, the Core Logic module forwards the commands to the keyboard controller. By default, the Core Logic module forces the deassertion of A20M# during a warm reset. This action may be disabled if F0 Index 52h[4] is cleared. Figure 5-10. SMI Generation for NMI PERR# IOCHK# F0 Index 04h[6] SERR# F0 Index 04h[8] F0 Index 40h[1] I/O Port 061h[2] I/O Port 061h[3] I/O Port 070h[7] Parity Errors AND System Errors NMI SMI F0 Index 04h: PCI Command Register Bit 6 = PE (PERR# Enable) Bit 8 = SE (SERR# Enable) F0 Index 40h: PCI Function Control Register 1 Bit 1 = PES (PERR# Signals SERR#) I/O Port 061h: Port B Bit 2 = ERR_EN (PERR#/SERR# Enable) Bit 3 = IOCHK_EN (IOCHK Enable) AND AND AND AND OR AND OR (No External Connection) |
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