XMEGAD datasheet(82/309 Pages) ATMEL

82 / 309 page

8210B–AVR–04/10

XMEGA D

8.3

Reset Sequence

Reset request from any reset source immediately reset the device, and keep it in reset as long

as the request is active. When all reset requests are released, the device will go through three

stages before the internal reset is released and the device starts running.

• Reset Counter Delay

• Oscillator startup

• Oscillator calibration

If one of the reset request occur during this, the reset sequence will start over again.

8.3.1

Reset Counter Delay

The Reset Counter Delay is the programmable period from all reset requests are released and

until the reset counter times out and releases reset. The Reset Counter Delay is timed from the

1 kHz output of the Ultra Low Power (ULP) Internal Oscillator, and the number of cycles before

the timeout is set by the STARTUPTIME fuse bits. The selectable delays are shown in Table 8-

8.3.2

Oscillator Startup

After the Reset Counter Delay, the default clock is started. This is the 2 MHz internal RC oscilla-

tor, and this uses 6 clock cycles to startup and stabilize.

8.3.3

Oscillator Calibration

After the default oscillator has stabilized, oscillator calibration values are loaded from Non-Vola-

tile Memory into the Oscillator Calibration registers. Loading the calibration values takes

24 clock cycles on the internal 2 MHz oscillator. The 2 MHz, 32 MHz and 32.768 kHz internal RC

oscillators are calibrated. When this is done the device will enter active mode and program exe-

cution will begin.

8.4

Reset Sources

8.4.1

Power-On Reset

A Power-on detection circuit will give a Power-On Reset (POR) when supply voltage (V

CC) is

applied to the device and the V

CC slope is increasing in the Power-on Slope Range (VPOSR).

Power-on reset is released when the V

CC stops rising or when the VCC level has reached the

Power-on Threshold Voltage (V

POT) level.

When V

CC is falling, the POR will issue a reset when the Vpot level is reached. The Vpot level is

lower than the minimum operating voltage for the device, and is only used for power-off function-

Table 8-1.

Reset Counter Delay

SUT[1:0]

Number of 1 kHz ULP oscillator clock cycles

Reserved

XMEGAD Datasheet(PDF) 82 Page - ATMEL Corporation

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