XMEGAD datasheet(5/309 Pages) ATMEL

5 / 309 page

8210B–AVR–04/10

XMEGA D

AVR CPU

3.1

Features

• 8/16-bit high performance AVR RISC CPU

– 138 instructions

– Hardware multiplier

• 32x8-bit registers directly connected to the ALU

• Stack in RAM

• Stack Pointer accessible in I/O memory space

• Direct addressing of up to 16M bytes of program memory and 16M bytes of data memory

• True 16/24-bit access to 16/24-bit I/O registers

• Efficient support for both 8-, 16- and 32-bit Arithmetic

• Configuration Change Protection of system critical features

3.2

Overview

XMEGA uses the 8/16-bit AVR CPU. The main function of the CPU is to ensure correct program

execution. The CPU is able to access memories, perform calculations and control peripherals.

Interrupt handling is described in a separate section, refer to ”Interrupts and Programmable

Multi-level Interrupt Controller” on page 95 for more details on this.

3.3

Architectural Overview

In order to maximize performance and parallelism, the AVR uses a Harvard architecture with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the Program Memory. This concept enables instructions to be executed

in every clock cycle. For the summary of all AVR instructions refer to ”Instruction Set Summary”

on page 296. For details of all AVR instructions refer to http://www.atmel.com/avr.

XMEGAD Datasheet(PDF) 5 Page - ATMEL Corporation