XMEGAD datasheet(97/309 Pages) ATMEL

97 / 309 page

8210B–AVR–04/10

XMEGA D

A return from an interrupt handling routine takes five clock cycles. During these five clock cycles,

the program counter is popped from the stack and the stack pointer is incremented.

10.5

Interrupt level

The interrupt level is independently selected for each interrupt source. For any interrupt request,

the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre-

sponding bit values for the interrupt level configuration of all interrupts is shown in Table 10-1.

The interrupt level of an interrupt request is compared against the current level and status of the

interrupt controller. An interrupt request on higher level will interrupt any ongoing interrupt han-

dler from a lower level interrupt. When returning from the higher level interrupt handler, the

execution of the lower level interrupt handler will continue.

10.6

Interrupt priority

Within each interrupt level, all interrupts have a priority. When several interrupt requests are

pending, the order of which interrupts are acknowledged is decided both by the level and the pri-

ority of the interrupt request. Interrupts can be organized in a static or dynamic (round-robin)

priority scheme. High and Medium level interrupts and the NMI will always have static priority.

For Low level interrupts, static or dynamic priority scheduling can be selected.

10.6.1

Static priority

Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector

address decides the priority within one interrupt level where the lowest interrupt vector address

has the highest priority. Refer to the device datasheet for interrupt vector table with the base

address for all modules and peripherals with interrupt. Refer to the interrupt vector summary of

each module and peripheral in this manual for a list of interrupts and their corresponding offset

address within the different modules and peripherals.

Table 10-1.

Interrupt level

configuration

Group Configuration

Description

OFF

Interrupt disabled.

Low level interrupt

MED

Medium level interrupt

High level interrupt

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