XMEGAD datasheet(95/309 Pages) ATMEL

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8210B–AVR–04/10

XMEGA D

10. Interrupts and Programmable Multi-level Interrupt Controller

10.1

Features

• Separate interrupt vector for each interrupt

• Short, predictable interrupt response time

• Programmable Multi-level Interrupt Controller

– 3 programmable interrupt levels

– Selectable priority scheme within low level interrupts (round-robin or fixed)

– Non-Maskable Interrupts (NMI)

• Interrupt vectors can be moved to the start of the Boot Section.

10.2

Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execu-

tion. Peripherals can have one or more interrupts, and all are individually enabled. When the

interrupt is enabled and the interrupt condition is present this will generate a corresponding inter-

rupt request. All interrupts have a separate interrupt vector address.

The Programmable Multi-level Interrupt Controller (PMIC) controls the handling of interrupt

requests, and prioritizing between the different interrupt levels and interrupt priorities. When an

interrupt request is acknowledged by the PMIC, the program counter is set to point to the inter-

rupt vector, and the interrupt handler can be executed.

All peripherals can select between three different priority levels for their interrupts; low, medium

or high. Medium level interrupts will interrupt low level interrupt handlers. High level interrupts

will interrupt both medium and low level interrupt handlers. Within each level, the interrupt prior-

ity is decided from the interrupt vector address, where the lowest interrupt vector address has

the highest interrupt priority. Low level interrupts have an optional round-robin scheduling

scheme to ensure that all interrupts are serviced within a certain amount of time.

Non-Maskable Interrupts (NMI) are also supported.

10.3

Operation

Interrupts must be globally enabled for any interrupts to be generated. This is done by setting

the global interrupt enable bit (I-bit) in the CPU Status Register. The I-bit will not be cleared

when an interrupt is acknowledged. Each interrupt level must also be enabled before interrupts

with the corresponding level can be generated.

When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the

interrupt request. Based on the interrupt level and interrupt priority of any ongoing interrupts, the

interrupt is either acknowledged or kept pending until it has priority. When the interrupt request

is acknowledged, the program counter is updated to point to the interrupt vector. The interrupt

vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.

After returning from the interrupt handler, program execution continues from where it was before

the interrupt occurred. One instruction is always executed before any pending interrupt is

served.

The PMIC status register contains state information that ensures that the PMIC returns to the

correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an

interrupt handler. Returning from an interrupt will return the PMIC to the state it had before enter-

ing the interrupt. The Status Register (SREG) is not saved automatically upon an interrupt

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