GX1 datasheet(182/247 Pages) NSC

182 / 247 page

www.national.com

182

Revision 1.0

Power Management (Continued)

5.3

POWER MANAGEMENT REGISTERS

The GX1 processor contains the power management reg-

isters for the serial packet transmission control, the user-

defined power management address space, Suspend

Refresh, and SMI status for Suspend/Resume. These

registers are memory mapped (GX_BASE+8500h-8FFFh)

in the address space of the GX1 processor and are

described in the following sections. Refer to Section 4.1.2

“Control Registers” on page 99 for instructions on access-

ing these registers.

Note, however, the PM_BASE and PM_MASK registers

areaccessedwiththe CPU_READ andCPU_WRITE

instructions.

Refer

Section

4.1.6

“CPU_READ/

CPU_WRITE Instructions” on page 102 for more informa-

tion regarding these instructions.

Table 5-1 summarizes the above mentioned registers.

Tables 5-2 and 5-3 give these register’sbit formats.

Table 5-1. Power Management Register Summary

GX_BASE+

Memory Offset

Type

Name/Function

Default

Value

Control and Status Registers

8500h-8503h

R/W

PM_STAT_SMI

PM SMI Status register: Contains System Management Mode (SMM) status infor-

mation used by SoftVGA.

xxxxxx00h

8504h-8507h

R/W

PM_CNTRL_TEN

PM Serial Packet Control register: Sets the serial packet transmission frequency

and enables specific CPU events to be recorded in the serial packet.

xxxxxx00h

8508h-850Bh

R/W

PM_CNTRL_CSTP

PM Clock Stop Control register: Enables the 3V Suspend Mode for the GX1 pro-

cessor.

xxxxxx00h

850Ch-850Fh

R/W

PM_SER_PACK

PM Serial Packet register: Transmits the contents of the serial packet.

xxxxxx00h

Programmable Address Region Registers

FFFFFF6Ch

R/W

PM_BASE

PM Base register: Contains the base address for the programmable memory

range decode. This register, in combination with the PM_MASK register, is used to

generate a memory range decode which sets bit 1 in the serial transmission

packet.

00000000h

FFFFFF7Ch

R/W

PM_MASK

PM Mask register: The address mask for the PM_BASE register

00000000h

Table 5-2. Power Management Control and Status Registers

Bit

Name

Description

GX_BASE+8500h-8503h

PM_STAT_SMI Register (R/W)

Default Value = xxxxxx00h

31:8

RSVD

Reserved: These bits are not used. Do not write to these bits.

7:3

RSVD

Reserved: Set to 0.

2SMI_MEM

SMI VGA Emulation Memory: This bit is set high if a SMI was generated for VGA emulation in

response to a VGA memory access. An SMI can be generated on a memory access to one of three

regions in the A0000h to BFFFFh range as specified in the BC_XMAP_1 register. (See Table 4-9 on

page 104)

1SMI_IO

SMI VGA Emulation I/O: This bit is set high if a SMI was generated for VGA emulation in response

to an I/O access. An SMI can be generated on a I/O access to one of three regions in the 3B0h to

3DFh range as specified in the BC_XMAP_1 register. (See Table 4-9 on page 104)

0SMI_PIN

SMI Pin: When set high, this bit indicates that the SMI# input pin has been asserted to the

GX1 processor.

Note:

These bits are “sticky” bits and can only be cleared with a write of ‘1’ to the respective bit.

GX1 Datasheet(PDF) 182 Page - National Semiconductor (TI)

GX1 Datasheet(HTML) 182 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL