GX1 datasheet(186/247 Pages) NSC

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186

Revision 1.0

Electrical Specifications (Continued)

6.2

ELECTRICAL CONNECTIONS

6.2.1

Power/Ground Connections and Decoupling

Testing and operating the GX1 processor requires the use

of standard high frequency techniques to reduce parasitic

effects. These effects can be minimized by filtering the DC

power leads with low-inductance decoupling capacitors,

using low-impedance wiring, and by connecting all VCC2

and VCC3 pins to the appropriate voltage levels.

6.2.1.1

Power Planes

Figure 6-1 shows layout recommendations for splitting the

power plane between VCC2 (core: 1.6V, 1.8V, 2.0V) and

VCC3 (I/O: 3.3V) volts in the BGA package. The illustration

assumes there is one power plane, and no components on

the back of the board.

Figure 6-2 shows layout recommendations for splitting the

power plane between VCC2 (core: 1.6V, 1.8V, 2.0V) and

VCC3 (I/O: 3.3V) volts in the SPGA package.

Figure 6-1. BGA Recommended Split Power Plane and Decoupling

= High frequency capacitor

= 220 µF, low ESR capacitor

= 3.3V connection

= 1.6V, 1.8V, or 2.0V connection

352 BGA - Top View

1.6V, 1.8V, or 2.0V Plane

(VCC2)

3.3V Plane

(VCC3)

3.3V Plane

(VCC3)

3.3V Plane

(VCC3)

1.6V, 1.8V, or 2.0V Plane

(VCC2)

Legend

Geode™ GX1

Processor

3.3V Plane

(VCC3)

Note: Where signals cross plane splits, it is recommended to include

AC decoupling between planes with 47 pF capacitors.

GX1 Datasheet(PDF) 186 Page - National Semiconductor (TI)

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