BT8376EPF datasheet(236/323 Pages) CONEXANT

236 / 323 page

Bt8370/8375/8376

3.17 System Bus Registers

Fully Integrated T1/E1 Framer and Line Interface

3-118

Conexant

N8370DSE

TSYN_NEG

Output Sync on Falling Edge Clock—Selects TSBCKI rising or falling edge clock signal for

TFSYNC or TMSYNC outputs. Opposite TSBCKI edge is used if TFSYNC or TMSYNC is

programmed as input.

0 = TFSYNC or TMSYNC rising edge output (falling edge input)

1 = TFSYNC or TMSYNC falling edge output (rising edge input)

When TFSYNC or TMSYNC is an input and configured for rising edge sampling,

TFSYNC or TMSYNC must be sampled low during the previous falling clock edge, then

sampled high at the rising clock edge. (Refer to Figure 5-5, SBI Timing: Setup and Hold Time

for RFSYNC/RMSYNC and TFSYNC/TMSYNC Input Signals and Table 5-6, Input Data Setup

and Hold Timing.)

TSB_ALIGN

Transmit System Bus Multiframe Aligns to Transmit Timebase—Allows multiframe

alignment located at TX timebase to pass across TSLIP and forces the corresponding

multiframe alignment onto the TSB timebase. Used primarily to pass CAS or MFAS alignment

located by the transmit online framer onto the TMSYNC output.

0 = TSB multiframe does not follow XMTR

1 = TSB multiframe aligned by XMTR

TSB_CTR

Force TSLIP to Center—Writing a 1 to TSB_CTR forces TSLIP read buffer pointer to its

initial delay condition, possibly forcing a change of transmit frame alignment if TSLIP is

configured in Elastic or Bypass modes. Writing a 0 has no effect. The processor must assert

TSB_CTR after configuration of the transmit slip buffer, after which, Bt8370/8375/8376

automatically recenters TSLIP buffer according to the configured mode. Centering TSLIP

does not effect TSLIP status reported in ISR5[addr 006].

0 = no effect

1 = force TSLIP to center

TSBI[1:0]

Transmit Slip Buffer Interface mode—Selects the configuration of the TSLIP buffer. The TSBI

determines the total buffer depth and initial delay conditions. While TSLIP is bypassed, TCKI

clocks the TSB input/output, and TSBCKI is ignored.

To guarantee the pointer is initialized properly in the slip buffer during Elastic Mode,

the following procedure can be applied:

Disable Slip Buffer

TSBI[1:0] = 11, TSB_CTR = 0

Center Slip Buffer

TSBI[1:0] = 11, TSB_CTR = 1

Set the Slip Buffer to Elastic mode

TSBI[1:0] = 10, TSB_CTR = 0

TSBI

Mode

Total Depth

Initial Delay

Conditions

Normal

2 Frame

0.5 to 1.5 Frames

Dependent on present depth, no

change of output frame.

Short

2 Frame

32 Bits

Reverts to normal upon slip

Elastic

64 Bits

32 Bits

Recenters automatically upon slip

Bypass

0 Bits

TSBCKI ignored

NOTE(S):

Bypass requires system bus equal to line rate.

BT8376EPF Datasheet(PDF) 236 Page - Synaptics Incorporated.

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