BT8376EPF datasheet(239/323 Pages) CONEXANT

239 / 323 page

Bt8370/8375/8376

Fully Integrated T1/E1 Framer and Line Interface

3.17 System Bus Registers

N8370DSE

Conexant

3-121

0D7—Receive Signaling Configuration (RSIG_CR)

SET_RSIG

Force RSIG Interrupt—Allows the processor to receive an interrupt on RSIG [addr 008] at

every multiframe boundary. Applicable only to T1 mode. Overrides STACK interrupt.

0 = RSIG interrupt on signaling STACK change

1 = RSIG interrupts on T1 multiframe boundary

SET_SIG

Overwrite Robbed-Bit Signaling—Applicable only during T1 mode and function dependent

on RIDLE. When RIDLE is inactive, SET_SIG forces receive robbed-bit signaling to one

before updating the RSLIP time slot value. Bit 8 of each time slot received during signaling

frames 6, 12, 18, and 24 is replaced with a 1. This function is particularly useful in

cross-connect and exchange systems that strip robbed-bit signaling, or in systems that use

different signaling frame alignment on inbound and outbound ports.

0 = no change to receive signaling

1 = replace robbed-bit signaling

UNICODE

Inband Signaling Freeze (applicable to T1 modes only)—If UNICODE is enabled, received

ABCD signaling on all channels is searched on a per-channel basis for the 4-bit UNICODE

pattern. UNICODE pattern detection inhibits STACK and RSIG buffer updates for that

channel as long as UNICODE is present, but does not affect SIGFRZ output. It is not reported

to the processor. This function is described in Bellcore TR-TSY-000303, Section 4.4.9, Revision

2, July 1989.

0 = no effect

1 = enable UNICODE detection and per-channel signaling freeze

DEBOUNCE

Debounce Receive ABCD Signaling—Applicable only to those channels where the signaling

stack is enabled (SIG_STK; addr 180–19F). The signaling buffer (RSIG) output updates for

these channels are evaluated after D-bit signaling is received. New signaling is placed into

RSIG and STACK buffers only if the RSIG input and output values differ. The DEBOUNCE

function filters single bit errors in ABCD signaling by comparing incoming bits, buffered bits

from the previous multiframe, and output bits on a bit-by-bit basis. A signaling error is

detected if the new input signaling and current output signaling are the same but differ from

the current buffered signaling. When this occurs, the current buffered signaling is rejected, and

the output signaling does not change. Therefore, output signaling is updated only when the

current buffered signaling and the input signaling are equal. At the end of each multiframe, the

entire input ABCD value is copied to the output ABCD value.

0 = no effect

1 = debounce receive ABCD signaling

—

SET_RSIG

SET_SIG

UNICODE

DEBOUNCE

FRZ_OFF

FRZ_ON

THRU

BT8376EPF Datasheet(PDF) 239 Page - Synaptics Incorporated.

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