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BT8376EPF Datasheet(PDF) 240 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 240 Page - Synaptics Incorporated. |
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240 / 323 page  Bt8370/8375/8376 3.17 System Bus Registers Fully Integrated T1/E1 Framer and Line Interface 3-122 Conexant N8370DSE FRZ_OFF/FRZ_ON Manual Signaling Update and SIGFRZ Output—Allows the processor to manually control updates of the receive signaling buffer [RSIGn; addr 1A0–1BF], the signaling stack [addr 0DA], and the SIGFRZ output pin. FRZ_ON and FRZ_OFF control the SIGFRZ pin’s output state, but do not affect normal operations of the SIGFRZ interrupt [ISR7; addr 004]. The receive ABCD input signaling is placed into the STACK and RSIG buffers according to the modes shown below. Stack updates are individually enabled on a per-channel basis according to SIG_STK [addr 180–19F]. THRU Enable Transparent Robbed-Bit Signaling—RMSYNC is forced to align with respect to RX timebase and follow each change of receiver's multiframe alignment, plus any frame offset caused by RSLIP buffer delay. In this manner, RMSYNC is able to retain its signaling multiframe alignment with respect to RPCMO output data frames. THRU mode is required when RSLIP is configured in Bypass mode. It is also useful for ADPCM transcoder systems that utilize robbed-bit signaling during frames other than normal (modulo 6) signaling frames, and therefore cannot utilize RPCMO signaling reinsertion in ADPCM coded channels. During THRU mode, RMSYNC must be programmed as an output [PIO; addr 018]. RMSYNC can follow a change of RX multiframe alignment without generating an alarm indication (e.g., receiver change of SF alignment without accompanying loss of basic frame alignment). 0 = no effect 1 = transparent robbed-bit signaling Signaling State During Current Multiframe Signaling State Updated at the End of Current Multiframe New Input Signaling Bit Buffered Input Signaling Bit from Previous Multiframe (RSIGn[3:0]) Buffered Output Signaling Bit (RSIGn[7:4]) Buffered Input Signaling Bit is Updated from Input Signaling Bit (RSIGn[3:0]) Buffered Output Signaling Bit (RSIGn[7:4]) Notes 00 00 0 10 01 0 1 1 0 1 1 Change Output 0 1 0 0 0 Debounce 11 11 1 01 10 1 0 0 1 0 0 Change Output 1 0 1 1 1 Debounce NOTE(S): Non-Debounced signaling always transfers buffered ABCD input to buffered ABCD output coincident with the D-bit update. SIGFRZ FRZ_ON FRZ_OFF SIG_STK Interrupt Pin STACK RSIGn 0 0 0 0 0 No update All ABCD 0 0 X 1 1 No update No update 0 0 1 0 0 ABCD Changes All ABCD X 1 0 X 0 No Update All ABCD X 1 1 X 0 ABCD Changes All ABCD 1 0 X X 1 No update No Update |
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