HC05 datasheet(53/232 Pages) MOTOROLA

53 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

3-11

MEMORY AND REGISTERS

3.8

Miscellaneous register

POR — Power-on reset bit (see Section 10.1)

This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the

user to make a software distinction between a power-on and an external reset. This bit cannot be

set by software and is cleared by writing it to zero.

1 (set)

–

A power-on reset has occurred.

0 (clear) –

No power-on reset has occurred.

INTP, INTN — External interrupt sensitivity options (see Section 10.2)

These two bits allow the user to select which edge the IRQ pin and WOI will be sensitive to (see

Table 3-4). Both bits can be written to only while the I-bit is set, and are cleared by power-on or

external reset, thus the device is initialised with negative edge and low level sensitivity.

INTE — External interrupt enable (see Section 10.2)

1 (set)

–

External interrupt function (IRQ) enabled.

0 (clear) –

External interrupt function (IRQ) disabled.

The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,

thus enabling the external interrupt function.

SFA — Slow or fast mode selection for PLMA (see Section 8.1)

1 (set)

–

Slow mode PLMA (4096 x timer clock period).

0 (clear) –

Fast mode PLMA (256 x timer clock period).

(1) The POR bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Miscellaneous

$000C

POR(1)

INTP

INTN

INTE

SFA

SFB

WDOG(2) u001 000u

Table 3-4 IRQ and WOI sensitivity

INTP

INTN

IRQ sensitivity

WOI interrupt options

Negative edge and low level sensitive

Positive edge and high level sensitive

Negative edge only

Positive edge only

Negative edge only

Positive and negative edge sensitive

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