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HC05 Datasheet(PDF) 78 Page - Motorola, Inc

Part # HC05
Description  High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
PDF  232 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

HC05 Datasheet(HTML) 78 Page - Motorola, Inc

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MOTOROLA
5-16
MC68HC05X16
Rev. 1
MOTOROLA CAN MODULE (MCAN)
5
5.3.8
MCAN bus timing register 1 (CBT1)
This register can only be accessed when the reset request bit in the CCNTRL register is set.
SAMP — Sampling
This bit determines the number of samples of the serial bus to be taken per bit time. When set three
samples per bit are taken. This sample rate gives better rejection of noise on the bus, but
introduces a one bit delay to the bus sampling. For higher bit rates SAMP should be cleared, which
means that only one sample will be taken per bit.
1 (set)
–
Three samples per bit.
0 (clear) –
One sample per bit.
TSEG22 – TSEG10 — Time segment bits
Time segments within the bit time fix the number of clock cycles per bit time, and the location of
the sample point.
SYNC_SEG
System expects transitions to occur on the bus during this period.
Transmit point
A node in transmit mode will transfer a new value to the MCAN bus at this point.
Sample point
A node in receive mode will sample the bus at this point. If the three samples per
bit option is selected then this point marks the position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 5-3.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of
bus clock cycles (tSCL) per bit (as shown above).
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
MCAN bus timing 1 (CBT1)
$0027
SAMP TSEG22 TSEG21 TSEG20TSEG13TSEG12TSEG11TSEG10 Undefined
Figure 5-5 Segments within the bit time
TSEG 1
BIT_TIME
SYNC_SEG
TSEG 2
SYNC_SEG
1 clock cycle
tSCL
Sample point
Transmit point
Transmit point
76



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