HC05 datasheet(69/232 Pages) MOTOROLA

69 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

5-7

MOTOROLA CAN MODULE (MCAN)

RIE — Receive interrupt enable

1 (set)

–

Enabled – The CPU will get an interrupt request whenever a

message has been received free of errors.

0 (clear) –

Disabled – The CPU will get no receive interrupt request.

RR — Reset request

When the MCAN detects that RR has been set it aborts the current transmission or reception of a

message and enters the reset state. A reset request may be generated by either an external reset

or by the CPU or by the MCAN. The RR bit can be cleared only by the CPU. After the RR bit has

been cleared, the MCAN will start normal operation in one of two ways. If RR was generated by

an external reset or by the CPU, then the MCAN starts normal operation after the ﬁrst occurrence

of 11 recessive bits. If, however, the RR was generated by the MCAN due to the BS bit being set

(see Section 5.3.3) the MCAN waits for 128 occurrences of 11 recessive bits before starting

normal operation.

A reset request should not be generated by the CPU during a message transmission. Ensure that

a message is not being transmitted as follows:

if TCS in CSTAT is clear – set AT in CCOM (use STA or STX), read CSTAT.

if TS in CSTAT is set – wait until TS is clear.

Note that a CPU-generated reset request does not change the values in the transmit and receive

error counters.

1 (set)

–

Present – MCAN will be reset.

0 (clear) –

Absent – MCAN will operate normally.

Note:

The following registers may only be accessed when reset request = present: CACC,

CACM, CBT0, CBT1, and COCNTRL.

5.3.2

MCAN command register (CCOM)

This is a write only register; a read of this location will always return the value $FF.

This register may be written only when the RR bit in CCNTRL is clear.

Do not use read-modify-write instructions on this register (e.g. BSET, BCLR).

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Reset

condition

State

on reset

MCAN command (CCOM) $0020

RX0

RX1 COMPSEL SLEEP COS

RRB

External reset 00u0 0000

RR bit set

00u0 0000

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