HC05 datasheet(94/232 Pages) MOTOROLA

94 / 232 page

MOTOROLA

6-6

MC68HC05X16

Rev. 1

PROGRAMMABLE TIMER

6.2.2

Timer status register (TSR)

The timer status register ($13) contains the status bits corresponding to the timer interrupt

conditions – ICF1, OCF1, TOF, ICF2 and OCF2.

Accessing the timer status register satisﬁes the ﬁrst condition required to clear the status bits. The

remaining step is to access the register corresponding to the status bit.

ICF1 — Input capture ﬂag 1

This bit is set when the selected polarity of edge is detected by the input capture edge detector 1

at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading

the TSR and then the input capture low register 1 ($15).

1 (set)

–

A valid input capture has occurred.

0 (clear) –

No input capture has occurred.

OCF1 — Output compare ﬂag 1

This bit is set when the output compare 1 register contents match those of the free-running

counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading

the TSR and then the output compare 1 low register ($17).

1 (set)

–

A valid output compare has occurred.

0 (clear) –

No output compare has occurred.

TOF — Timer overﬂow status ﬂag

This bit is set when the free-running counter overﬂows from $FFFF to $0000; a timer overﬂow interrupt

will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($19).

1 (set)

–

Timer overﬂow has occurred.

0 (clear) –

No timer overﬂow has occurred.

When using the timer overﬂow function and reading the free-running counter at random times to

measure an elapsed time, a problem may occur whereby the timer overﬂow ﬂag is unintentionally

cleared if:

The timer status register is read or written when TOF is set, and

The LSB of the free-running counter is read, but not for the purpose of

servicing the ﬂag.

Reading the alternate counter register instead of the counter register will avoid this potential

problem.

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Timer status (TSR)

$0013

ICF1

OCF1

TOF

ICF2

OCF2

Undeﬁned

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