HC05 datasheet(11/232 Pages) MOTOROLA

11 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

iii

TABLE OF CONTENTS

Paragraph

Number

Page

Number

TITLE

4.5.1

Port data registers A and B (PORTA and PORTB) .......................................... 4-4

4.5.2

Port data register C (PORTC).......................................................................... 4-5

4.5.3

Port data register D (PORTD).......................................................................... 4-5

4.5.4

A/D status/control register ............................................................................... 4-5

4.5.5

Data direction registers (DDRA, DDRB and DDRC)........................................ 4-6

4.6

Other port considerations ...................................................................................... 4-6

MOTOROLA CAN MODULE (MCAN)

5.1

TBF – Transmit buffer ............................................................................................ 5-4

5.2

RBF – Receive buffer ............................................................................................ 5-4

5.3

Interface to the MC68HC05X16 CPU .................................................................... 5-4

5.3.1

MCAN control register (CCNTRL) ................................................................... 5-6

5.3.2

MCAN command register (CCOM) .................................................................. 5-7

5.3.3

MCAN status register (CSTAT) ........................................................................ 5-10

5.3.4

MCAN interrupt register (CINT) ....................................................................... 5-12

5.3.5

MCAN acceptance code register (CACC)........................................................ 5-13

5.3.6

MCAN acceptance mask register (CACM) ...................................................... 5-14

5.3.7

MCAN bus timing register 0 (CBT0) ................................................................ 5-14

5.3.8

MCAN bus timing register 1 (CBT1) ................................................................ 5-16

5.3.9

MCAN output control register (COCNTRL)...................................................... 5-18

5.3.10

Transmit buffer identiﬁer register (TBI)............................................................. 5-20

5.3.11

Remote transmission request and data length code register (TRTDL)............ 5-20

5.3.12

Transmit data segment registers (TDS) 1 – 8 .................................................. 5-21

5.3.13

Receive buffer identiﬁer register (RBI) ............................................................. 5-21

5.3.14

Remote transmission request and data length code register (RRTDL) ........... 5-22

5.3.15

Receive data segment registers (RDS) 1 – 8 .................................................. 5-22

5.4

Interface to the MCAN bus .................................................................................... 5-22

5.4.1

Single wire operation ....................................................................................... 5-24

5.5

Sleep mode ........................................................................................................... 5-24

5.5.1

Sleep comparator reference ............................................................................ 5-25

PROGRAMMABLE TIMER

6.1

Counter.................................................................................................................. 6-1

6.1.1

Counter register and alternate counter register ............................................... 6-3

6.2

Timer control and status ........................................................................................ 6-4

6.2.1

Timer control register (TCR) ............................................................................ 6-4

6.2.2

Timer status register (TSR) ............................................................................. 6-6

6.3

Input capture.......................................................................................................... 6-7

6.3.1

Input capture register 1 (ICR1) ........................................................................ 6-7

6.3.2

Input capture register 2 (ICR2) ........................................................................ 6-8

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