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HC05 Datasheet(PDF) 34 Page - Motorola, Inc |
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HC05 Datasheet(HTML) 34 Page - Motorola, Inc |
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34 / 232 page ![]() MOTOROLA 2-10 MC68HC05X16 Rev. 1 MODES OF OPERATION AND PIN DESCRIPTIONS 2 2.2.3.1 Miscellaneous register SM — Slow mode 1 (set) – The system runs at a bus speed 16 times lower than normal (fOSC/32, /64, /128 or /160). SLOW mode affects all sections of the device (including SCI, A/D and timer) except for the MCAN module. 0 (clear) – The system runs at normal bus speed (fOSC/2, /4, /8 or /10). The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when entering STOP mode. Note: The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in Section 3.8. Figure 2-5 Slow mode divider block diagram Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG u001 000u OSC1 pin OSC2 pin Oscillator fOSC Control logic SM–bit ÷ 2, 4, Main internal clock (bit 1, $000C) MCAN Note: The MCAN module clock is unaffected during SLOW mode. 8 and 10 ÷ 2 ÷ 16 32 |
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