HC05 datasheet(91/232 Pages) MOTOROLA

91 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

6-3

PROGRAMMABLE TIMER

6.1.1

Counter register and alternate counter register

The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter

of the free-running counter ($19 or $1B) receives the count value at the time of the read. If a read

of the free-running counter or alternate counter register ﬁrst addresses the more signiﬁcant byte

(MSB) ($18 or $1A), the LSB is transferred to a buffer. This buffer value remains ﬁxed after the ﬁrst

MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the

free-running counter or alternate counter register LSB and thus completes a read sequence of the

total counter value. In reading either the free-running counter or alternate counter register, if the

MSB is read, the LSB must also be read to complete the sequence. If the timer overﬂow ﬂag (TOF)

is set when the counter register LSB is read then a read of the timer status register (TSR) will clear

the ﬂag.

The alternate counter register differs from the counter register only in that a read of the LSB does

not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overﬂow

interrupts due to clearing of TOF, the alternate counter register should be used.

The free-running counter is set to $FFFC during power-on and external reset and is always a

read-only register. During a power-on reset, the counter begins running after the oscillator start-up

delay. Because the free-running counter is 16 bits preceded by a ﬁxed divide-by-4 prescaler, the

value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when

the counter overﬂows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.

In some particular timing control applications it may be desirable to reset the 16-bit free running

counter under software control. When the low byte of the counter ($19 or $1B) is written to, the

counter is conﬁgured to its reset value ($FFFC).

The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of

the ﬂags and enable bits remain unaltered by this operation. If access has previously been made

to the high byte of the free-running counter ($18 or $1A), then the reset counter operation

terminates the access sequence.

Warning: This operation may affect the function of the watchdog system (see Section 10.1.4).

The PLM results will also be affected while resetting the counter.

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Timer counter high

$0018

1111 1111

Timer counter low

$0019

1111 1100

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Alternate counter high

$001A

1111 1111

Alternate counter low

$001B

1111 1100

HC05 Datasheet(PDF) 91 Page - Motorola, Inc

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