HC05 datasheet(17/232 Pages) MOTOROLA

17 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

LIST OF FIGURES

Figure

Number

Page

Number

TITLE

LIST OF FIGURES

1-1

MC68HC05X16 block diagram ............................................................................... 1-4

2-1

Bootstrap mode function selection ﬂow chart......................................................... 2-2

2-2

MC68HC05X16 ‘jump to any address’ schematic diagram..................................... 2-4

2-3

MC68HC05X16 ‘load program in RAM and execute’ schematic diagram............... 2-5

2-4

STOP and WAIT ﬂow charts................................................................................... 2-9

2-5

Slow mode divider block diagram ........................................................................... 2-10

2-6

Oscillator connections ............................................................................................ 2-14

2-7

Oscillator divider block diagram.............................................................................. 2-15

3-1

Memory map of the MC68HC05X16 ...................................................................... 3-2

3-2

MCAN module memory map .................................................................................. 3-3

4-1

Standard I/O port structure..................................................................................... 4-2

4-2

ECLK timing diagram ............................................................................................. 4-3

4-3

Port logic levels ...................................................................................................... 4-7

5-1

MCAN block diagram.............................................................................................. 5-1

5-2

MCAN frame formats.............................................................................................. 5-2

5-3

MCAN module memory map .................................................................................. 5-5

5-4

Oscillator block diagram ......................................................................................... 5-15

5-5

Segments within the bit time .................................................................................. 5-16

5-6

A typical physical interface between the MCAN and the MCAN bus lines ............. 5-23

6-1

16-bit programmable timer block diagram .............................................................. 6-2

6-2

Timer state timing diagram for reset....................................................................... 6-13

6-3

Timer state timing diagram for input capture .......................................................... 6-13

6-4

Timer state timing diagram for output compare...................................................... 6-14

6-5

Timer state timing diagram for timer overﬂow......................................................... 6-14

7-1

Serial communications interface block diagram ..................................................... 7-2

7-2

SCI rate generator division ..................................................................................... 7-4

7-3

Data format............................................................................................................. 7-5

7-4

SCI examples of start bit sampling technique ........................................................ 7-7

7-5

SCI sampling technique used on all bits ................................................................ 7-7

7-6

Artiﬁcial start following a framing error ................................................................... 7-8

7-7

SCI start bit following a break................................................................................. 7-8

7-8

SCI example of synchronous and asynchronous transmission .............................. 7-9

7-9

SCI data clock timing diagram (M=0) ..................................................................... 7-12

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