HC05 datasheet(86/232 Pages) MOTOROLA

86 / 232 page

MOTOROLA

5-24

MC68HC05X16

Rev. 1

MOTOROLA CAN MODULE (MCAN)

If several CAN modules are driving a dominant level on the bus at the same time then the values

for VCANH and VCANL can go to 0.3 and 4.7 volts respectively. The residual 0.3 V is due to the

voltage drop across the diodes and driver transistors in the transmission circuit.

The receiver part of the network uses two identical voltage divider networks, with a divide ratio of

6:1 (resistor values of 150k

Ω and 30kΩ) referenced to V

DD/2. This increases the common mode

range of the input comparator on the physical bus lines. If the common mode range of the

comparator at its inputs is 1.5 to 3.5 volts then, for VDD = 5.0 V, the common mode range will be

increased to –3.5 to +8.5 volts on the bus lines.

5.4.1

Single wire operation

In the event of a bus fault occurring, limited operation of the MCAN bus may still be possible,

depending on the nature of the fault. If the fault is due to a short circuit between the two bus lines

or between one of the lines and ground, battery voltage or some other potential, it is possible to

identify (using a special software procedure) the line on which the fault exists and to switch the

corresponding comparator input from the faulty line to the VDD/2 reference supply. At the same

time the driver transistors to the faulty line should also be switched off. This will allow

communication to continue on the bus. One result of this mode of one wire transmission is a

signiﬁcant reduction in the common mode range of the input comparator.

Switching to one wire operation is achieved using the control bits RX0-passive and RX1-passive

in the MCAN command register, located at address $21. Setting either of these bits will result in

the corresponding input being disconnected from the bus and connected to VDD/2.

5.5

Sleep mode

If the SLEEP bit in the MCAN command register is set by the processor the MCAN will go to sleep,

unless it is active. If there is activity on the MCAN bus lines, or there is an interrupt pending, the

MCAN is deemed to be active and will not go to sleep; a wake-up interrupt will be generated by

the MCAN in these circumstances. The SLEEP bit may also be cleared by the processor, in which

case no wake-up interrupt will be generated. Note that this bit is write-only by the CPU, and it is

not possible therefore to check whether sleep mode has been entered by reading it. However, the

CAF bit in the EEPROM control register is set when the MCAN is asleep, and cleared when it is

woken up (see Section 3.5.1).

In order to minimize power consumption, the active comparator is switched off and the sleep

comparator circuitry is used to detect activity on the bus. When in sleep mode the MCAN stops its

own clocks, leaving the MCU in normal run mode. (Similarly a STOP instruction will stop the

processor clocks, leaving the MCAN in run mode.) The on-chip oscillator will stop only if the MCAN

is in sleep mode and the MCU executes a STOP instruction. There is a time delay between the

STOP instruction being executed and the oscillator stopping. During this time it is possible that the

MCAN will come out of sleep mode, and hence prevent the oscillator from stopping.

HC05 Datasheet(PDF) 86 Page - Motorola, Inc

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