BT8376EPF datasheet(138/323 Pages) CONEXANT

138 / 323 page

3.0 Registers

Bt8370/8375/8376

3.4 Interrupt Status Registers

Fully Integrated T1/E1 Framer and Line Interface

3-20

Conexant

N8370DSE

RSIG

Receive Signaling Stack—Indicates 1 or more signaling bit changes were detected during the

prior receive multiframe, and new ABCD (robbed bit or CAS) signaling is available on the

Receive Signaling Stack register [addr 0DA]. RSIG is cleared by processor read of ISR3,

independent of STACK contents. See also the SET_RSIG bit (addr 0D7).

0 = no stack update

1 = new ABCD signaling

RMSYNC

Receive System Bus MF Sync—Activated every 1.5 ms (SF/SLC), 3 ms (ESF), or 2 ms

(CAS), coincident with the first bit of receive system bus multiframe output on RPCMO.

0 = no timer event

1 = RSB multiframe

RMF

Receive Multiframe Boundary—Activated every 3 ms for T1 (Ft, SF, SLC, ESF), or 2 ms

(MFAS), coincident with the first bit of a received multiframe. If MFAS is not included in the

receive framer criteria, RMF is activated at 2 ms interval.

0 = no timer event

1 = receive multiframe

RFRAME

Receive Frame Boundary—Activated every 193 bits (T1) or 256 bits (E1), coincident with the

first bit of a received frame. The processor can read RPHASE [addr 0DB] to determine which

RSLIP buffer half can be accessed.

0 = no timer event

1 = receive frame

009—Data Link 1 Interrupt Status (ISR2)

All events in ISR2 are from rising edge sources. Each event is latched active-high and held until the processor

read clears ISR2. Each event triggers an interrupt if the corresponding IER2 bit is enabled [addr 011].

TBOP

BOP Codeword Transmitted—Set when a valid Bit Oriented Codeword has been transmitted

and a new TBOP value can be written [TBOP; addr 0A1].

RFULL1

Receive FIFO Full—In HDLC modes, RFULL is set when the data link receiver attempts to

write received data to a full FIFO causing the receive data link FIFO to overrun. In

unformatted modes (Pack6 and Pack8), RFULL is set when the receive FIFO is filled to the

MSG_FILL Limit selected in register RDL1_FFC [addr 0A7].

RNEAR1

Receive FIFO Near Full—Set when the receive FIFO fill level reaches the near full threshold

selected in register RDL1_FFC [addr 0A7].

RMSG1

Message Received—Set when a complete message or a partial message is received and

available in the receiver FIFO.

TDLERR1

Transmit FIFO Error—Set when the FIFO underruns as a result of the internal logic emptying

the FIFO without encountering an end of message [TDL1_EOM; addr 0AC]. The underrun

condition also forces transmission of an HDLC abort code.

TEMPTY1

Transmit FIFO Empty—Set when the FIFO overflows as a result of the processor attempting to

write to a full FIFO. Overflow data is ignored by the transmit FIFO.

TNEAR1

Transmit FIFO Near Empty —Set when the transmit FIFO level falls below the threshold

selected in register TDL1_FEC [addr 0AB].

TMSG1

Message Transmitted—Set when a complete message has been transmitted and the closing flag

is just beginning transmission.

TBOP

RFULL1

RNEAR1

RMSG1

TDLERR1

TEMPTY1

TNEAR1

TMSG1

BT8376EPF Datasheet(PDF) 138 Page - Synaptics Incorporated.

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