BT8376EPF datasheet(170/323 Pages) CONEXANT

170 / 323 page

Bt8370/8375/8376

3.8 Receiver Registers

Fully Integrated T1/E1 Framer and Line Interface

3-52

Conexant

N8370DSE

RLOF_INTEG

Enable RLOF Integration—When set, the receive loss of frame status [RLOF; addr 047] is

integrated for 2.0 to 2.5 seconds during T1 framer modes (not applicable to E1 modes). RLOF

interrupt status [ISR7; addr 004] is also integrated. However, receive framer status in ALM3

[addr 049], loss of frame count [FRED[3:0]; addr 05A] and RLOF counter overflow [ISR4;

addr 007] are unaffected. RLOF_INTEG does not meet the requirements of TR62411. To meet

the requirements of TR62411 “Conditions Causing The Initiation of Carrier Failure Alarms,”

the receive loss of frame condition reported by FRED (addr 049) must be integrated before

initiating Yellow Alarm Transmission. This can be accomplished in software by integrating

FRED during an RLOF Interrupt (ISR7; addr 004), with RLOF_INTEG bit cleared.

0 = normal RLOF status

1 = integrated RLOF [addr 047] status

RPCM_AIS

Send AIS on RPCMO Output Pin—Replaces RPCMO data with a continuous series of all 1s.

RPCM_AIS is useful in CSU or digital section applications, where the local interface must be

able to forward an AIS to the opposing interface.

0 = normal RPCMO data

1 = RPCMO replaced with all ones

046—Alarm/Error/Counter Latch Configuration (LATCH)

STOP_CNT

Stop Error Count during RLOF/RLOS/RAIS—When enabled, error count registers [addr

050–057] are suspended at their present values during one of the following conditions: receive

loss of frame (RLOF), loss of signal (RLOS), or all 1s (RAIS) alarm condition. STOP_CNT

does not affect the counting of test pattern errors [BERR; addr 058, 059] or alarm events

[AERR; addr 05A]. The occurrence of a red or AIS CGA inhibits further processing of all

other performance parameters (i.e., BER, errored seconds, SLIPS). However, a CGA caused

by a Yellow Alarm does not inhibit further alarm or performance monitoring.

0 = Continue error count during alarms

1 = Stop error count during alarms

LATCH_CNT

Enable ONESEC Latching of Counters—Determines the interval for which error counts

remain held in all count registers [addr 050–057]. LATCH_CNT must be active in T1 mode

whenever automatic 1-second performance report messaging [AUTO_PRM; addr 0AA] is

enabled. LATCH_CNT is active during E1 mode; the processor cannot use the RLOF counter

overflow [addr 007] as a 128 ms MFAS timeout.

When the LATCH_CNT is inactive, the processor read of the LSB register reports the

current LSB error count, it latches the current MSB error count to the MSB register, and then it

clears LSB. Subsequently, reading the MSB register reports current latched MSB error count

and then clears MSB.

————

STOP_CNT

LATCH_CNT

LATCH_ERR

LATCH_ALM

LATCH_CNT

Count Latched

Count Hold Time

Never

Until read clear

ONESEC interval

BT8376EPF Datasheet(PDF) 170 Page - Synaptics Incorporated.

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