BT8376EPF datasheet(210/323 Pages) CONEXANT

210 / 323 page

Bt8370/8375/8376

3.16 Data Link Registers

Fully Integrated T1/E1 Framer and Line Interface

3-92

Conexant

N8370DSE

0A5—DL1 Bit Enable (DL1_BIT)

DL1_BIT[7:0]

DL1 Bit Select—Works in conjunction with DL1_TS [addr 0A4] to select one or more time

slot bits for data link input and output. Any combination of bits can be enabled by writing the

corresponding DL1_BIT active (high). The LSB enables first bit transmitted or received, and

MSB enables eighth bit transmitted or received. DL1_BIT has no effect when DL1_TS selects

T1 F-bits.

0 = disable data link bit

1 = enable data link bit

0A6—DL1 Control (DL1_CTL)

TDL1_RPT

The Circular Buffer/FIFO control bit [TDL1_RPT; addr 0A6] allows the FIFO to act as a

circular buffer; in this mode, a message can be transmitted repeatedly. This feature is available

only for unformatted transmit data link applications. The processor can repeatedly send fixed

patterns on the selected channel by writing a 1- to 64-byte message into the circular buffer. The

programmed message length repeats until the processor writes a new message. The first byte of

each unformatted message is output automatically, aligned to the first frame of a 24-, or

16-frame transmit multiframe (SF/ESF/MFAS). This allows the processor to source overhead

or data elements aligned to the TX timebase. In both SF and ESF T1 modes, unformatted

messages are aligned on 24-frame boundaries. Therefore, in SF applications, the repeating

message must be designed to span two SF multiframes. Each unformatted message written is

output-aligned only after the preceding message completes transmission. Therefore, data

continuity is retained during the linkage of consecutive messages, provided that the contents of

each message consist of a multiple of the multiframe length.

DL1[1: 0]

Data Link 1 mode—Selects either HDLC-formatted Frame Check Sequence (FCS) or

Non-FCS transmit and receive data link message mode or unformatted (Pack8 or Pack6)

message mode. During HDLC modes, the transmit/receive circuits perform zero

insertion/removal after each occurrence of five consecutive 1s contained in the message bits,

FLAG (0x7E) character insertion/removal during idle channel conditions, and ABORT (0xFF)

code insertion/detection upon errored channel conditions. Refer to ITU-T Recommendation

Q.921 for complete details of the HDLC link-layer protocol. FCS mode automatically

generates, inserts, and checks the 16-bit FCS without passing FCS bits through transmit and

receive FIFOs. Non-FCS mode passes all message bits that exist between the opening and

closing FLAG characters through the FIFOs, without generating or checking FCS bits.

Non-FCS mode allows the processor to generate and check the entire contents of each HDLC

frame.

Unformatted data link modes provide transparent channel access, in which every data link

bit transmitted is supplied by the processor through TDL1, and each bit received is passed to

the processor through RDL1 [addr 0A8]. Pack8 and Pack6 unformatted mode options select

the number of bits per byte that are stored in transmit/receive FIFOs—8 or 6 bits, respectively.

DL1_BIT[7]

DL1_BIT[6]

DL1_BIT[5]

DL1_BIT[4]

DL1_BIT[3]

DL1_BIT[2]

DL1_BIT[1]

DL1_BIT[0]

———

TDL1_RPT

DL1[1]

DL1[0]

TDL1_EN

RDL1_EN

BT8376EPF Datasheet(PDF) 210 Page - Synaptics Incorporated.

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