AD9166 datasheet(33/138 Pages) AD

33 / 138 page

Data Sheet

AD9166

Rev. 0 | Page 33 of 138

Figure 52 and Figure 53 are provided as points of reference for

hardware designers and show the insertion loss for various

lengths of well laid out stripline and microstrip transmission

lines, respectively. See the Hardware Considerations section for

specific layout recommendations for the JESD204B channel.

Low power mode is recommended if the insertion loss of the

JESD204B PCB channels is less than that of the most lossy

supported channel for low power mode (shown in Figure 51). If

the insertion loss is greater than that, but still less than that of

the most lossy supported channel for normal mode (shown in

Figure 51), use normal mode. At 12.5 Gbps operation, the

equalizer in normal mode consumes about 4 mW more power

per lane than in low power equalizer mode. Note that either mode

can be used in conjunction with transmitter preemphasis to

ensure functionality and/or optimize for power.

FREQUENCY (GHz)

6.250

9.375

3.125

AD9166 ALLOWED

CHANNEL LOSS

(NORMAL MODE)

AD9166 ALLOWED

CHANNEL LOSS

(LOW POWER MODE)

JESD204B SPEC ALLOWED

CHANNEL LOSS

EXAMPLE OF

JESD204B

COMPLIANT

CHANNEL

EXAMPLE OF

AD9166

COMPATIBLE

CHANNEL (LOW

POWER MODE)

EXAMPLE OF

AD9166

COMPATIBLE

CHANNEL

(NORMAL MODE)

Figure 51. Insertion Loss Allowed

–40

–35

–30

–25

–20

–15

–10

–5

123

FREQUENCY (GHz)

STRIPLINE = 6"

STRIPLINE = 10"

STRIPLINE = 15"

STRIPLINE = 20"

STRIPLINE = 25"

STRIPLINE = 30"

Figure 52. Insertion Loss of 50 Ω Striplines on FR4

–40

–35

–30

–25

–20

–15

–10

–5

FREQUENCY (GHz)

STRIPLINE = 6"

STRIPLINE = 10"

STRIPLINE = 15"

STRIPLINE = 20"

STRIPLINE = 25"

STRIPLINE = 30"

Figure 53. Insertion Loss of 50 Ω Microstrips on FR4

÷2

÷8

PCLK

GENERATOR

÷4, ÷2,

OR ÷1

CDR OVERSAMP

REG 0x289

PLL REF CLOCK

VALID RANGE

35MHz TO 80MHz

SAMPLE CLOCK

I, Q TO CDR

VALID RANGE

3GHz TO 6.25GHz

ENABLE HALF RATE

DIVISION RATE

REG 0x230

JESD LANE CLOCK

(SAME RATE AS PCLK)

INTERPOLATION

JESD LANES

REG 0x110

PLL_REF_CLK_RATE

1×, 2×, 4×

REG 0x084

DAC CLOCK

÷6 TO ÷127,

DEFAULT: 10

CDR

÷N

÷4

MODE

HALF RATE

FULL RATE, NO DIV

FULL RATE, DIV 2

FULL RATE, DIV 4

DIVIDE (N)

160

Figure 54. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block

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