AD9166 datasheet(11/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 11 of 138

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

NOISE SPECTRAL DENSITY (NSD)

Single tone, IOUTFS = 40 mA

fOUT = 537 MHz

−157

dBc/Hz

fOUT = 1044 MHz

−157

dBc/Hz

fOUT = 2062 MHz

−157

dBc/Hz

fOUT = 3791 MHz

−154

dBc/Hz

fOUT = 4095 MHz

−157

dBc/Hz

fOUT = 5011 MHz

−153

dBc/Hz

fOUT = 5926 MHz

−150

dBc/Hz

SINGLE SIDEBAND PHASE NOISE AT OFFSET

fOUT = 3600 MHz, fDAC = 12,042.24 MSPS

1 kHz Offset

−110.2

dBc/Hz

10 kHz Offset

−134.8

dBc/Hz

100 kHz Offset

−140.4

dBc/Hz

1 MHz Offset

−149.0

dBc/Hz

10 MHz Offset

−154.0

dBc/Hz

1 See the Clock Input section for more details on optimizing SFDR and reducing the image of the fundamental with clock input tuning.

CMOS PIN SPECIFICATIONS

DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,

DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC =3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3V, AMP_N5 = −5.0 V,

IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. CS_x refers to CS_AMP and CS_DAC.

Table 8.

Parameter

Symbol

Test Comments/Conditions

Min

Typ

Max

Unit

INPUTS (SDIO, SCLK, CS_x, RESET, TX_ENABLE)

Voltage Input

High

VIH

1.8 V ≤ VDD_IO ≤ 2.5 V

0.7 × VDD_IO

Low

VIL

1.8 V ≤ VDD_IO ≤ 2.5 V

0.3 × VDD_IO

Current Input

High

IIH

μA

Low

IIL

−150

μA

OUTPUTS (SDIO, SDO)

Voltage Output

High

VOH

1.8 V ≤ VDD_IO ≤ 3.3 V

0.8 × VDD_IO

Low

VOL

1.8 V ≤ VDD_IO ≤ 3.3 V

0.2 × VDD_IO

Current Output

High

IOH

Low

IOL

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