AD9166 datasheet(8/138 Pages) AD

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AD9166

Data Sheet

Rev. 0 | Page 8 of 138

JESD204B INTERFACE SPECIFICATIONS

DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,

DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,

IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. VTT is the termination voltage.

Table 4.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SERIAL INTERFACE SPEED

Guaranteed operating range per each lane

Half Rate

12.5

Gbps

Full Rate

6.25

Gbps

Oversampling

1.5

3.125

Gbps

2× Oversampling

0.750

1.5625

Gbps

JESD204B DATA INPUTS

Input Leakage Current

TA = 25°C

Logic High

Input level = 1.2 V ± 0.25 V, VTT = 1.2 V

μA

Logic Low

Input level = 0 V

−4

μA

Unit Interval

1333

Common-Mode Voltage

VRCM

AC-coupled, VTT = DAC_1P2_SER1

−0.05

+1.85

Differential Voltage

VDIFF

110

1050

VTT Source Impedance

ZTT

At dc

Differential Impedance

ZRDIFF

At dc

100

120

Differential Return Loss

RLRDIF

Common-Mode Return Loss

RLRCM

SYSREF± INPUT

Differential Impedance

121

DIFFERENTIAL OUTPUTS (SYNCOUT±)2

Driving 100 Ω differential load

Output Differential Voltage

VOD

350

420

450

Output Offset Voltage

VOS

1.15

1.2

1.27

1 As measured on the input side of the ac coupling capacitor.

2 IEEE Standard 1596.3 LVDS compatible.

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