AD9166 datasheet(44/138 Pages) AD

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AD9166

Data Sheet

Rev. 0 | Page 44 of 138

A value of yes in Table 27 means the interpolation rate is supported

for the number of lanes. A blank cell means it is not supported.

Table 27. Interpolation Rates and Number of Lanes

Interpolation

1×

Yes1

2×

Yes

Yes1

3×

Yes

4×

Yes

Yes1

6×

Yes

8×

Yes

12×

Yes

16×

Yes

24×

Yes

1 These modes restrict the maximum device clock rate to 5 GHz.

Configuration Parameters

The AD9166 modes refer to the link configuration parameters

for L, K, M, N, NP, S, and F. Table 28 provides the description

and addresses for these settings.

Table 28. Configuration Parameters

JESD204B

Setting

Description

Address

L − 1

Number of lanes minus 1.

Bits[4:0]

F − 1

Number of ((octets per frame) per

lane) minus 1.

Bits[7:0]

K − 1

Number of frames per multiframe

minus 1.

Bits[4:0]

M − 1

Number of converters minus 1.

Bits[7:0]

N − 1

Converter bit resolution minus 1.

Bits[4:0]

NP − 1

Bit packing per sample minus 1.

Bits[4:0]

S − 1

Number of ((samples per

converter) per frame) minus 1.

Bits[4:0]

High density format. Set to 1 if F =

1. Leave at 0 if F ≠ 1.

0x45A, Bit 7

DID

Device ID. Match the device ID

sent by the transmitter.

Bits[7:0]

BID

Bank ID. Match the bank ID sent by

the transmitter.

Bits[7:0]

LID0

Lane ID for Lane 0. Match the Lane

ID sent by the transmitter on

Logical Lane 0.

Bits[4:0]

JESDV

JESD204x version. Match the

version sent by the transmitter

(0x0 = JESD204A, 0x1 =

JESD204B).

Bits[7:5]

Data Flow Through the JESD204B Receiver

The link configuration parameters determine how the serial bits

on the JESD204B receiver interface are deframed and passed on

to the DACs as data samples.

Deskewing and Enabling Logical Lanes

After proper configuration, the logical lanes are automatically

deskewed. All logical lanes are enabled or not based on the lane

number setting in Register 0x110, Bits[7:4]. The physical lanes

are all powered up by default.

To disable power to physical lanes that are not being used, set Bit x

in Register 0x201 to 1 to disable Physical Lane x, and keep it at 0

to enable it.

JESD204B TEST MODES

PHY PRBS Testing

The JESD204B receiver on the AD9166 includes a pseudorandom

binary sequence (PRBS) pattern checker on the back end of its

physical layer. This functionality enables bit error rate (BER)

testing of each physical lane of the JESD204B link. The PHY

PRBS pattern checker does not require that the JESD204B link be

established. The pattern checker can synchronize with a PRBS7,

PRBS15, or PRBS31 data pattern. The PRBS pattern can be

verified on multiple lanes simultaneously. The error counts for

failing lanes are reported for one JESD204B lane at a time.

Table 29. PHY PRBS Pattern Selection

PHY_PRBS_PAT_SEL Setting

(Register 0x316, Bits[3:2])

PRBS Pattern

0b00 (default)

PRBS7

0b01

PRBS15

0b10

PRBS31

The process for performing PRBS testing on the AD9166 is as

follows, using Table 29 for reference.

Start sending a PRBS7, PRBS15, or PRBS31 pattern from

the JESD204B transmitter.

Select and write the appropriate PRBS pattern to

Enable the PHY test for all lanes being tested by writing to

PHY_TEST_EN (Register 0x315). Each bit of Register 0x315

enables the PRBS test for the corresponding lane. For example,

writing a 1 to Bit 0 enables the PRBS test for Physical Lane 0.

Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0

to 1 then back to 0.

Set PHY_PRBS_TEST_THRESHOLD_xBITS (Bits[23:0],

Write a 0 and then a 1 to PHY_TEST_START (Register 0x316,

Bit 1). The rising edge of PHY_TEST_START starts the test.

(Optional) In some cases, it may be necessary to

repeat Step 4 at this point. Toggle PHY_TEST_RESET

(Register 0x316, Bit 0) from 0 to 1, then back to 0.

Wait 500 ms.

Stop the test by writing PHY_TEST_START

(Register 0x316, Bit 1) = 0.

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