AD9166 datasheet(9/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 9 of 138

INPUT DATA RATE AND BANDWIDTH SPECIFICATIONS

DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,

DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,

IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

INPUT DATA RATE

Complex1

Interpolation > 1×

0.15

2.5

GSPS

Real

Interpolation = 1×

0.3

5.0

GSPS

INSTANTANEOUS SIGNAL BANDWIDTH2

Complex

fCLK = 5 GHz, interpolation = 2×

2.25

GHz

fCLK = 6 GHz, interpolation = 3×

1.8

GHz

Real

fCLK = 5 GHz, interpolation = 1×

2.5

GHz

ANALOG BANDWIDTH

2x NRZ (FIR85 Enabled)

fDAC = 12.0 GSPS

Minimum

GHz

Maximum

9.0

GHz

Mix Mode (FIR85 Disabled)

fDAC = 6.0 GSPS

Minimum

1.0

GHz

Maximum

8.0

GHz

NRZ (FIR85 Disabled)

fDAC = 6.0 GSPS

Minimum

GHz

Maximum3

4.5

GHz

1 The complex data rate is the combined rate for both I and Q.

2 Interpolation filter bandwidth set to 90%.

3 Limited by the available output power due to sinc roll-off. See Figure 88 for more details.

PIPELINE DELAY AND LATENCY UNCERTAINTY SPECIFICATIONS

DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,

DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,

IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Table 6.

Parameter1

Test Conditions/Comments

Min

Typ

Max

Unit

JESD204B LINK LATENCY

Fixed

PCLK2 cycles

Variable

PCLK2 cycles

JESD204B TO DATAPATH INTERFACE LATENCY

PCLK2 cycle

DATAPATH PIPELINE DELAY3

NCO only, FIR85 off, inverse sinc off

fCLK cycles

SYSREF± to LOCAL MULTIFRAME CLOCKS (LMFC) DELAY

JED204B Subclass 1

fCLK cycles

DETERMINISTIC LATENCY UNCERTAINTY

JED204B Subclass 0

fCLK cycles

JED204B Subclass 14

fCLK cycles

1 The total latency through the device is calculated as follows:

Total Latency = Fixed Latency + Variable Latency + Interface Latency + Datapath Pipeline Delay.

2 PCLK is the internal processing clock for the AD9166 and equals the lane rate ÷ 40.

3 See Table 33 for pipeline delay (latency) values across different datapath configurations.

4 The SYSREF± signal input is sampled at a rate of fCLK/4, which leads to up to 4 fCLK cycles of deterministic latency uncertainty, provided that the setup and hold times for

sampling SYSREF± are met according to Table 10. The deterministic latency uncertainty can be further improved, using Register 0x037 and Register 0x038 to read the

exact clock cycle that was used to sample SYSREF±. See the SYSREF± Signal section for more details.

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