AD9166 datasheet(27/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 27 of 138

SERIAL PORT OPERATION

The AD9166 includes two separate SPI controllers, one for the

DAC and one for the amplifier. Either the DAC or the amplifier

can be addressed using the same SDIO, SDO, and SCLK pins,

while asserting the corresponding chip select pin, CS_AMP or

CS_DAC. CS_AMP and CS_DAC cannot be asserted

simultaneously to address both the DAC and the amplifier

during the same communication cycle, as described in the Chip

Select (CS_AMP and CS_DAC) section.

The serial port is a flexible, synchronous serial communications

port that allows easy interfacing with many industry-standard

microcontrollers and microprocessors. The serial input/output

(I/O) is compatible with most synchronous transfer formats,

including both the Motorola SPI and Intel® SSR protocols. The

interface allows read/write access to all registers that configure

the AD9166. MSB first or LSB first transfer formats are supported.

The serial port interface can be configured as a 4-wire interface

or a 3-wire interface in which the input and output share a single-

pin I/O (SDIO).

SCLK

SDO

SIO

CS_AMP

SPI

PORT

J14

J13

J12

M13

CS_DAC

B14

Figure 43. Serial Port Interface Pins

There are two phases to a communication cycle with the AD9166.

Phase 1 is the instruction cycle (the writing of an instruction

byte into the device), coincident with the first 16 SCLK rising

edges. The instruction word provides the serial port controller

with information regarding the data transfer cycle, Phase 2 of

the communication cycle. The Phase 1 instruction word defines

whether the upcoming data transfer is a read or write, along with

the starting register address for the following data transfer.

A logic high on the pin followed by a logic low resets the serial

port timing to the initial state of the instruction cycle. From this

state, the next 16 rising SCLK edges represent the instruction

bits of the current I/O operation.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one or more data bytes. Eight × N SCLK cycles are

needed to transfer N bytes during the transfer cycle. Registers

change immediately upon writing to the last bit of each transfer

byte, except for the FTW and NCO phase offsets, which change

only when the frequency tuning word FTW_LOAD_REQ bit is set.

A logic high on CS_AMP or CS_DAC followed by a logic low

resets the serial port timing to the initial state of the instruction

cycle. From this state, the next 16 rising SCLK edges represent

the instruction bits of the current I/O operation.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and the

system controller. Phase 2 of the communication cycle is a transfer

of one or more data bytes. Eight × N SCLK cycles are needed to

transfer N bytes during the transfer cycle. Registers change

immediately upon writing to the last bit of each transfer byte,

except for the FTW and NCO phase offsets, which change only

when the frequency tuning word bit, FTW_LOAD_REQ, is set.

DATA FORMAT

The instruction byte contains the information listed in Table 14.

Table 14. Serial Port Instruction Word

I15 (MSB)

I[14:0]

R/W

A[14:0]

R/W, Bit I15 of the instruction word, determines whether a

read or a write data transfer occurs after the instruction word

write. Logic 1 indicates a read operation, and Logic 0 indicates a

write operation.

A14 to A0, Bit I14 to Bit I0 of the instruction word, determine

the register that is accessed during the data transfer portion of

the communication cycle. For multibyte transfers, A[14:0] is the

starting address. The remaining register addresses are generated

by the device based on the address increment bit. If the address

increment bits are set high (Register 0x000, Bit 5 and Bit 2), multi-

byte SPI writes start on A[14:0] and increment by 1 for every

eight bits sent or received. If the address increment bits are set

to 0, the address decrements by 1 every eight bits.

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 100 MHz. All data input is registered on the rising

edge of SCLK. All data is driven out on the falling edge of SCLK.

Chip Select (CS_AMP and CS_DAC)

The AD9166 includes two chip select pins, one for the DAC

(CS_DAC) and one for the buffer amplifier (CS_AMP),

hereafter referred to as CS_x. The correct CS_x pin must be

asserted to address the particular silicon die. CS_AMP and

CS_DAC cannot be asserted simultaneously.

An active low input starts and gates a communication cycle.

CS_x allows more than one device to be used on the same serial

communications line. The SDIO pin goes to a high impedance

state when this input is high. During the communication cycle,

the chip select must stay low.

Serial Data I/O (SDIO)

The SDIO pin is a bidirectional data line. In 4-wire mode, the

SDIO pin acts as the data input and the SDO pin acts as the data

output.

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