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AD9166 Datasheet(PDF) 49 Page - Analog Devices

Part # AD9166
Description  DC to 9 GHz Vector Signal Generator
PDF  138 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9166 Datasheet(HTML) 49 Page - Analog Devices

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Data Sheet
AD9166
Rev. 0 | Page 49 of 138
MAIN DIGITAL DATAPATH
HB
2×
HB
3×
JESD
HB
2×,
4×,
8×
NCO
INV
SINC
HB
2×
Figure 65. Block Diagram of the Main Digital Datapath
The block diagram in Figure 65 shows the functionality of the
main digital datapath. The digital processing includes an input
interpolation block with choice of bypass 1×, 2×, or 3× interpo-
lation, three additional 2× half-band interpolation filters, a final
2× NRZ mode interpolator filter, FIR85, that can be bypassed,
and a quadrature modulator that consists of a 48-bit NCO and
an inverse sinc block.
All of the interpolation filters accept I and Q data streams as a
complex data stream. Similarly, the quadrature modulator and
inverse sinc function also accept input data as a complex data
stream. Thus, any use of the digital datapath functions requires
the input data to be a complex data stream.
In bypass mode (1× interpolation), the input data stream is
expected to be real data.
Table 33. Pipeline Delay (Latency) for Various Datapath
Configurations
Mode
FIR85
On
Filter
Bandwidth
Inverse
Sinc
NCO
Pipeline Delay1
(fCLK Cycles)
NCO only
No
N/A2
No
Yes
48
1× (Bypass)
No
N/A2
No
No
113
1× (Bypass)
No
N/A2
Yes
No
137
2×
No
80%
No
No
155
2×
No
90%
No
No
176
2×
Yes
80%
No
No
202
2×
No
80%
Yes
No
185
2×
Yes
80%
Yes
No
239
2×
Yes
80%
Yes
Yes
279
3×
No
80%
No
No
168
3×
No
90%
No
No
202
4×
No
80%
No
No
308
6×
No
80%
No
No
332
8×
No
80%
No
No
602
12×
No
80%
No
No
674
16×
No
80%
No
No
1188
24×
No
80%
No
No
1272
1 The pipeline delay given is a representative number, and may vary by a cycle
or two based on the internal handoff timing conditions at startup.
2 N/A means not applicable.
The pipeline delay changes based on the digital datapath
functions that are selected. See Table 33 for examples of the
pipeline delay per block. These delays are in addition to the
JESD204B latency.
DATA FORMAT
The input data format for all modes on the AD9166 is 16-bit,
twos complement. The digital datapath and the DAC decoder
operate in twos complement format. The DAC is a current
steering DAC and cannot represent 0. The DAC must either
source or sink current. As a result, when the 0 of twos
complement is represented in the DAC, it is a +1, and all the
positive values thereafter are shifted by +1. This mapping error
introduces a ½ LSB shift in the DAC output. The leakage can
become apparent when using the NCO to shift a signal that is
above or below 0 Hz when synthesized. The NCO frequency is
seen as a small spur at the NCO frequency tuning word.
To avoid the NCO frequency leakage, operate the DAC with a
slight digital backoff of one or several codes, and then add 1 to
all values in the data stream. These actions remove the NCO
frequency leakage but cause a ½ LSB dc offset. This small dc
offset is benign to the DAC and does not affect most applications
because the DAC output is ac-coupled through dc blocking
capacitors.
INTERPOLATION FILTERS
The main digital path contains five half-band interpolation
filters, plus a final half-band interpolation filter that is used in
2× NRZ mode. The filters are cascaded, as shown in Figure 65.
The first pair of filters is a 2× (HB2) or 3× (HB3) filter. Each of
these filters has two options for bandwidth, 80% or 90%. The
80% filters are lower power than the 90% filters. The filters
default to the lower power 80% bandwidth. To select the filter
bandwidth as 90%, program the FILT_BW bit in the
DATAPATH_CFG register to 1 (Register 0x111, Bit 4 = 0b1).
Following the first pair of filters is a series of 2× half-band
filters, each of which halves the usable bandwidth of the
previous one. HB4 has 45%, HB5 has 22.5%, and HB6 has
11.25% of the fDATA bandwidth.
The final half-band filter, FIR85, is used in 2× NRZ mode.
FIR85 is clocked at the 2 × fCLK rate and has a usable bandwidth
of 45% of the fCLK rate. The FIR85 filter is a complex filter, and
therefore the bandwidth is centered at 0 Hz. The FIR85 filter is
used in conjunction with the complex interpolation modes to
allow doubling the DAC update rate, thus moving the image
spur further from the signal. Table 34 shows how to select each
available interpolation mode, their usable bandwidths, and their



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