AD9166 datasheet(61/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 61 of 138

ANALOG INTERFACE CONSIDERATIONS

ANALOG MODES OF OPERATION

The AD9166 DAC core uses the quad-switch architecture shown in

Figure 84. Only one pair of switches is enabled during a half-clock

cycle, thus requiring each pair to be clocked on alternative clock

edges. A key benefit of the quad-switch architecture is that it masks

the code dependent glitches that occur in the conventional two-

switch DAC architecture.

VG1

VSSA

IOUTP

IOUTN

VG1VG2VG3VG4

CLK±

CLK

LATCHES

DATA INPUT

VG2

VG3

VG4

NOTES

IOUTP AND IOUTN ARE THE POSITIVE AND NEGATIVE OUTPUT

CURRENTS, VGx IS THE GATE VOLTAGE, AND VSSA IS THE ANALOG

SUPPLY VOLTAGE.

Figure 84. Quad-Switch Architecture

In dual-switch architecture, when a switch transition occurs and

Data 1 and Data 2 (D1 and D2 in Figure 85) are in different

states, a glitch occurs. However, if D1 and D2 happen to be at the

same state, the switch transitions and no glitches occur. This

code dependent glitching causes an increased amount of

distortion in the DAC core. In quad-switch architecture (no

matter what the codes are), there are always two switches that

are transitioning at each half-clock cycle, thus eliminating the

code dependent glitches but creating a constant glitch at 2 × fDAC

in the process. For this reason, a significant clock spur at 2 × fDAC

is evident in the output spectrum of the core.

INPUT

DATA

DAC CLOCK

TWO-SWITCH

DAC OUTPUT

FOUR-SWITCH

DAC OUTPUT

(NORMAL MODE)

D1 D2 D3 D4 D5

D6 D7 D8 D9 D10

D1 D2 D3 D4 D5

D6 D7 D8 D9 D10

D1 D2

D4 D5

Figure 85. Two-Switch and Quad-Switch DAC Waveforms

As a consequence of the quad-switch architecture enabling updates

on each half-clock cycle, it is possible to operate the DAC core at

2× the expected DAC update rate (fS) if new data samples are

latched into the DAC core on both the rising and falling edge of the

device clock (fCLK). This notion serves as the basis when operating

the AD9166 in mix mode, RZ mode, or 2× NRZ mode. In each

case, the DAC core is presented with new data samples on each

clock edge. In RZ mode, the rising edge clocks data and the

falling edge clocks zero. In mix mode, the falling edge sample is

simply the complement of the rising edge sample value. In 2×

NRZ mode, both the rising edge and falling edge clock new data

samples. See the 2× NRZ Mode section for more details.

When mix mode is used, the output is effectively chopped at the

DAC sample rate. This chopping has the effect of reducing the

power of the fundamental signal while increasing the power of

the images centered around the DAC sample rate, thus improving

the dynamic range of these images.

INPUT

DATA

DAC CLOCK

FOUR-SWITCH

DAC OUTPUT

(

fS MIX MODE)

–D6

–D7

–D8

–D9

–D10

D10

–D1

–D2

–D3

–D4

–D5

D6 D7 D8 D9 D10

Figure 86. Mix Mode Waveform

This ability to change modes provides the user the flexibility to

place a carrier anywhere in the first three Nyquist zones, depending

on the operating mode selected. Switching between baseband

and mix mode reshapes the sinc roll-off inherent at the DAC

output. In baseband mode, the sinc null appears at fS because the

same sample latched on the rising clock edge is also latched again

on the falling clock edge, thus resulting in the same ubiquitous sinc

response of a traditional DAC. In mix mode, the complement

sample of the rising edge is latched on the falling edge, therefore

pushing the sinc null to 2 × fS. Figure 87 shows the ideal frequency

response of the three modes with the sinc roll-off included.

FREQUENCY (Hz)

1.50

1.25

1.00

0.75

0.50

0.25

–35

–30

–25

–20

–15

–10

–5

FIRST

NYQUIST ZONE

SECOND

NYQUIST ZONE

THIRD

NYQUIST ZONE

MIX MODE

RZ MODE

NORMAL

MODE

Figure 87. Sinc Roll-Off for NRZ, RZ, and Mix Mode Operation

The quad-switch can be configured via SPI (Register 0x152,

Bits[1:0]) to operate in either NRZ mode (0b00), RZ mode

(0b10), or mix mode (0b01).

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