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AD9166 Datasheet(PDF) 94 Page - Analog Devices

Part # AD9166
Description  DC to 9 GHz Vector Signal Generator
PDF  138 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9166 Datasheet(HTML) 94 Page - Analog Devices

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AD9166
Data Sheet
Rev. 0 | Page 94 of 138
Hex.
Addr.
Register Name
Bit
No.
Bit Name
Settings
Description
Reset
Access
3
SPI_CP_CAL_VALID_RB
This bit tells the user if the
charge pump calibration has
completed and is valid.
0x0
R
0 Charge pump calibration is
not valid.
1 Charge pump calibration is
valid.
[2:1] Reserved
Reserved.
0x0
R
0
SPI_PLL_LOCK_RB
If set, the SERDES synthesizer
is locked.
0x0
R
0 PLL is not locked.
1 PLL is locked.
0x289
REF_CLK_DIVIDER_LDO
[7:2] Reserved
Reserved.
0x0
R
[1:0] SERDES_PLL_DIV_FACTOR
SERDES PLL reference clock
division factor. This field
controls the division of the
SERDES PLL reference clock
before it is fed into the
SERDES PLL PFD. It must be
set so that fREF/division factor is
between 35 MHz and 80 MHz.
0x0
R/W
00 Divide by 4 for lane rate
between 6 Gbps and
12.5 Gbps.
01 Divide by 2 for lane rate
between 3 Gbps and 6 Gbps.
10 Divide by 1 for lane rate
between 1.5 Gbps and 3 Gbps.
0x2A7
TERM_BLK1_CTRLREG0
[7:1] Reserved
Reserved.
0x0
R
0
SPI_I_TUNE_R_CAL_TERMBLK1
Rising edge of this bit starts a
termination calibration
routine.
0x0
R/W
0x2A8
TERM_BLK1_CTRLREG1
[7:0] SPI_I_SERIALIZER_RTRIM_
TERMBLK1
SPI override for termination
value for PHY 0, PHY 1, PHY 6,
and PHY 7. Value options are
as follows:
0x0
R/W
XXX0XXXX Automatically calibrate
termination value.
XXX1000X Force 000 as termination value.
XXX1001X Force 001 as termination value.
XXX1010X Force 010 as termination value.
XXX1011X Force 011 as termination value.
XXX1100X Force 100 as termination value.
XXX1101X Force 101 as termination value.
XXX1110X Force 110 as termination value.
XXX1111X Force 111 as termination value.
XXX1000X Force 000 as termination value.
0x2AC
TERM_BLK1_RD_REG0
[7:4] Reserved
Reserved.
0x0
R
[3:0] SPI_O_RCAL_CODE_TERMBLK1
Readback of calibration code
for PHY 0, PHY 1, PHY 6, and
PHY 7.
0x0
R
0x2AE
TERM_BLK2_CTRLREG0
[7:1] Reserved
Reserved.
0x0
R
0
SPI_I_TUNE_R_CAL_TERMBLK2
Rising edge of this bit starts a
termination calibration
routine.
0x0
R/W



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