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AD9166 Datasheet(PDF) 90 Page - Analog Devices |
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AD9166 Datasheet(HTML) 90 Page - Analog Devices |
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90 / 138 page ![]() AD9166 Data Sheet Rev. 0 | Page 90 of 138 Hex. Addr. Register Name Bit No. Bit Name Settings Description Reset Access 0x200 MASTER_PD [7:1] Reserved Reserved. 0x0 R 0 SPI_PD_MASTER Powers down the entire JESD204B Rx analog (all eight channels and bias). 0x1 R/W 0x201 PHY_PD [7:0] SPI_PD_PHY SPI override to power down the individual PHYs. 0x0 R/W Bit 0 controls SERDIN0± PHY. Bit 1 controls SERDIN1± PHY. Bit 2 controls SERDIN2± PHY. Bit 3 controls SERDIN3± PHY. Bit 4 controls SERDIN4± PHY. Bit 5 controls SERDIN5± PHY. Bit 6 controls SERDIN6± PHY. Bit 7 controls SERDIN7± PHY. 0x203 GENERIC_PD [7:2] Reserved Reserved. 0x0 R 1 SPI_SYNC1_PD Powers down LVDS buffer for the sync request signal, SYNCOUT±. 0x0 R/W 0 Reserved Reserved. 0x0 R/W 0x206 CDR_RESET [7:1] Reserved Reserved. 0x0 R 0 SPI_CDR_RESET Resets the digital control logic for all PHYs. 0x1 R/W 0 CDR logic is reset. 1 CDR logic is operational. 0x230 CDR_OPERATING_MODE_ [7:6] Reserved Reserved. 0x0 R/W REG_0 5 SPI_ENHALFRATE Enables half rate CDR operation, must be enabled for data rates > 6 Gbps. 0x1 R/W 0 Disables CDR half rate operation, data rate ≤ 6 Gbps. 1 Enables CDR half rate operation, data rate > 6 Gbps. [4:3] Reserved Reserved. 0x1 R/W [2:1] SPI_DIVISION_RATE Enables oversampling of the input data. 0x0 R/W 00 No division. Data rate > 3 Gbps. 01 Division by 2. 1.5 Gbps < data rate ≤ 3 Gbps. 10 Division by 4. 750 Mbps < data rate ≤ 1.5 Gbps. 0 Reserved Reserved. 0x0 R/W 0x250 EQ_CONFIG_PHY_0_1 [7:4] SPI_EQ_CONFIG1 Controls equalizer boost level. 0x8 R/W 0000 Manual mode (SPI configured values used). 0001 Boost level = 1. 0010 Boost level = 2. 0011 Boost level = 3. 0100 Boost level = 4. 0101 Boost level = 5. 0110 Boost level = 6. 0111 Boost level = 7. 1000 Boost level = 8. 1001 Boost level = 9. 1010 Boost level = 10. 1011 Boost level = 11. 1100 Boost level = 12. |
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