AD9166 datasheet(83/138 Pages) AD

83 / 138 page

Data Sheet

AD9166

Rev. 0 | Page 83 of 138

Hex.

Addr.

Bit

No.

Bit Name

Settings

Description

Reset

Access

0x07F

CLK_PHASE_TUNE

[7:6] Reserved

Reserved.

0x0

[5:0] CLK_PHASE_TUNE

Fine tuning of the clock input

phase balance. Adds

capacitance to the CLK+ or

the CLK− input to phase shift

the differential input at CLK±.

The register is coded as signed

binary. Added nominal

capacitance =

CLK_PHASE_TUNE × 20 fF

0x0

R/W

Added Nominal Capacitance

At CLK+

At CLK−

0x0 0

0x1 20

0x2 40

… …

…

0x1F 620

0x20 0

0x21 0

0x22 0

… …

…

0x3F 0

620

0x080

CLK_PD

[7:1] Reserved

Reserved.

0x0

DACCLK_PD

Device clock power-down.

Powers down the device input

clock circuitry.

0x1

R/W

0Power up.

1Power down.

0x082

CLK_DUTY

CLK_DUTY_EN

Enable duty cycle control.

0x1

R/W

CLK_DUTY_OFFSET_EN

Enable duty cycle offset.

0x0

R/W

CLK_DUTY_BOOST_EN

Enable duty cycle range boost.

Extends range to ±5% at cost

of 1 dB to 2 dB worse phase

noise.

0x0

R/W

[4:0] CLK_DUTY_PRG

Program the duty cycle offset.

5-bit signed magnitude field,

with the MSB as the sign bit

and the four LSBs as the

magnitude from 0 to 15. A

larger magnitude skews duty

cycle to a greater amount.

Range is ±3%.

0x0

R/W

0x083

CLK_CRS_CTRL

CLK_CRS_EN

Enable clock cross control

adjustment.

0x1

R/W

[6:4] Reserved

Reserved.

0x0

[3:0] CLK_CRS_ADJ

Program the clock crossing

point.

0x0

R/W

0x084

PLL_REF_CLK_PD

[7:6] Reserved

Reserved.

0x0

[5:4] PLL_REF_CLK_RATE

PLL reference clock rate

multiplier.

0x0

R/W

00 Normal rate (1×) PLL reference

clock.

01 Double rate (2×) PLL reference

clock.

10 Quadruple rate (4×) PLL

reference clock.

11 Disable the PLL reference

clock.

[3:1] Reserved

Reserved.

0x0

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