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AD9166 Datasheet(PDF) 1 Page - Analog Devices |
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AD9166 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 138 page  DC to 9 GHz Vector Signal Generator Data Sheet AD9166 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents orother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES DC-coupled, 50 Ω matched output Up to 4.3 dBm output power, −9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2× NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2× NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2× NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2×, 3×, 4×, 6×, 8×, 12×, 16×, 24× Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2× interpolation) 1.8 GHz with device clock at 6 GHz (3× interpolation) Fast frequency hopping Integrated BiCMOS buffer amplifier APPLICATIONS Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers GENERAL DESCRIPTION The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/ deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended output buffer amplifier, matched to a 50 Ω load up to 10 GHz. The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning. The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband wave- form generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the most demanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power. The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter. In 2× nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz. In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2× NRZ mode. In baseband modes, such as return-to-zero (RZ) and 1× NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2× NRZ mode. The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones. The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns. The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm × 15 mm, 0.8 mm pitch BGA_ED package. PRODUCT HIGHLIGHTS 1. High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. 2. Fully supports zero IF and other dc-coupled applications. 3. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter. 1 Protected by U.S. Patents 6,842,132 and 7,796,971. |
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